[PATCH 3/5] x86/mce: Use msr_ops in prepare_msrs()
From: Smita Koralahalli <hidden>
Date: 2021-09-15 23:28:28
Also in:
lkml
Subsystem:
the rest, x86 architecture (32-bit and 64-bit), x86 mce infrastructure · Maintainers:
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, Tony Luck
Replace MCx_{STATUS, ADDR, MISC} macros with msr_ops.
Also, restructure the code to avoid multiple initializations for MCA
registers. SMCA machines define a different set of MSRs for MCA registers
and msr_ops initializes appropriate MSRs for SMCA and legacy processors.
Initialize MCA_MISC and MCA_SYND registers at the end after initializing
MCx_{STATUS, DESTAT} which is further explained in the next patch.
Make msr_ops exportable in order to be accessible from mce-inject module.
Signed-off-by: Smita Koralahalli <redacted>
---
arch/x86/kernel/cpu/mce/core.c | 1 +
arch/x86/kernel/cpu/mce/inject.c | 27 +++++++++++++--------------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 193204aee880..9af910acb930 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c@@ -222,6 +222,7 @@ struct mca_msr_regs msr_ops = { .addr = addr_reg, .misc = misc_reg }; +EXPORT_SYMBOL_GPL(msr_ops); static void __print_mce(struct mce *m) {
diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index 8de709b049fc..8af4c9845f96 100644
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c@@ -464,22 +464,21 @@ static void prepare_msrs(void *info) wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); - if (boot_cpu_has(X86_FEATURE_SMCA)) { - if (m.inject_flags == DFR_INT_INJ) { - wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); - wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); - } else { - wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); - wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); - } + if (boot_cpu_has(X86_FEATURE_SMCA) && + m.inject_flags == DFR_INT_INJ) { + wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); + wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); + goto out; + } + + wrmsrl(msr_ops.status(b), m.status); + wrmsrl(msr_ops.addr(b), m.addr); - wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); +out: + wrmsrl(msr_ops.misc(b), m.misc); + + if (boot_cpu_has(X86_FEATURE_SMCA)) wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); - } else { - wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); - wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); - wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); - } } static void do_inject(void)
--
2.17.1