Thread (6 messages) 6 messages, 3 authors, 2021-01-20

Re: [PATCH] EDAC/AMD64: Update scrub register addresses for newer models

From: Yazen Ghannam <yazen.ghannam@amd.com>
Date: 2021-01-20 14:47:42
Also in: lkml

On Mon, Jan 18, 2021 at 08:31:12PM +0100, Borislav Petkov wrote:
On Sat, Jan 16, 2021 at 02:33:53PM +0000, Yazen Ghannam wrote:
quoted
+static struct {
+	u32 base, limit;
+} f17h_scrub_regs = {F17H_M30H_SCR_BASE_ADDR, F17H_M30H_SCR_LIMIT_ADDR};
Why not make this part of struct amd64_umc so that you can access them
through pvt->umc?
We have a struct amd64_umc per channel, so putting these fixed values
there seemed redundant. Would you mind if we put this in struct
amd64_family_type? We can then set the values per family/model group
like we do with the max_mcs.

Thanks,
Yazen
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