Reject master clock rates outside the limits specified by the device.
External CMOS and LVDS clocks support 1.15 MHz to 34 MHz, while a
crystal requires 8 MHz to 34 MHz.
Signed-off-by: Janani Sunil <janani.sunil@analog.com>
---
drivers/iio/adc/ad7768.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c
index 3cb58c2554a3..44ba19fb2096 100644
--- a/drivers/iio/adc/ad7768.c
+++ b/drivers/iio/adc/ad7768.c
@@ -91,6 +91,9 @@
#define AD7768_SPI_REG_MASK GENMASK(14, 8)
#define AD7768_SPI_DATA_MASK GENMASK(7, 0)
+#define AD7768_MIN_MCLK_FREQ_HZ (1150 * HZ_PER_KHZ)
+#define AD7768_MIN_XTAL_FREQ_HZ (8 * HZ_PER_MHZ)
+#define AD7768_MAX_MCLK_FREQ_HZ (34 * HZ_PER_MHZ)
#define AD7768_MAX_CHANNEL 8
enum ad7768_clock_source {@@ -807,6 +810,23 @@ static void ad7768_power_off(void *data)
dev_err(dev, "Failed to put device to sleep\n");
}
+static int ad7768_validate_mclk_rate(struct device *dev,
+ const struct ad7768_state *st)
+{
+ unsigned long min_rate = AD7768_MIN_MCLK_FREQ_HZ;
+ unsigned long rate = clk_get_rate(st->mclk);
+
+ if (st->clock_source == AD7768_CLOCK_SOURCE_XTAL)
+ min_rate = AD7768_MIN_XTAL_FREQ_HZ;
+
+ if (rate < min_rate || rate > AD7768_MAX_MCLK_FREQ_HZ)
+ return dev_err_probe(dev, -EINVAL,
+ "MCLK rate %lu Hz outside %lu-%lu Hz\n",
+ rate, min_rate, AD7768_MAX_MCLK_FREQ_HZ);
+
+ return 0;
+}
+
static int ad7768_probe(struct spi_device *spi)
{
unsigned int spi_readback, rev_id;@@ -882,6 +902,10 @@ static int ad7768_probe(struct spi_device *spi)
return dev_err_probe(dev, PTR_ERR(st->mclk),
"Failed to get master clock\n");
+ ret = ad7768_validate_mclk_rate(dev, st);
+ if (ret)
+ return ret;
+
st->regmap = devm_regmap_init(dev, &ad7768_regmap_bus, spi,
st->chip_info->regmap_config);
if (IS_ERR(st->regmap))
--
2.43.0