[PATCH v48 6/7] arm64: dts: imx8ulp: add secure enclave node
From: <hidden>
Date: 2026-09-04 09:22:43
Also in:
imx, linux-arm-kernel, linux-devicetree, lkml
Subsystem:
arm/freescale imx / mxc / layerscape arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
From: Pankaj Gupta <pankaj.gupta@nxp.com> Add the EdgeLock Enclave (ELE) secure-enclave node to the i.MX8ULP SoC dtsi, together with a label for sram@2201f000 that the node references. Keep the node disabled in the SoC dtsi so it does not impose a reserved-memory requirement on every board. Boards enable the enclave and provide its memory-region by including imx8ulp-firmware.dtsi. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 777b89ed6849..ac8293f81c6b 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi@@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2021 NXP + * Copyright 2021, 2025 NXP */ #include <dt-bindings/clock/imx8ulp-clock.h>
@@ -154,7 +154,7 @@ sosc: clock-sosc { #clock-cells = <0>; }; - sram@22010000 { + sram0: sram@22010000 { compatible = "mmio-sram"; reg = <0x0 0x22010000 0x0 0x10000>;
@@ -186,6 +186,14 @@ scmi_sensor: protocol@15 { #thermal-sensor-cells = <1>; }; }; + + hsm0: secure-enclave { + compatible = "fsl,imx8ulp-se-ele-hsm"; + mbox-names = "tx", "rx"; + mboxes = <&s4muap 0 0>, <&s4muap 1 0>; + sram = <&sram0>; + status = "disabled"; + }; }; cm33: remoteproc-cm33 {
--
2.43.0