Re: [PATCH v19 04/14] KVM: arm64: Ensure GCS memory effects are visible

On Wed, Aug 12, 2026 at 08:12:03PM +0100, Mark Brown wrote:

In order to allow efficient implementation of GCS implementations are
permitted to do GCS specific caching, with barriers implicit in stack
switch operations

(GCSSS2)

and GCSB DSYNC as an explicit barrier.  Since we do
not use GCS in the hypervisor or host kernel the hypervisor cannot rely
on any barriers being present in vCPU context switches other than those
it explicitly inserts.  Add explicit barriers when loading and saving
vCPU state.

The same way we have a DSB, having a GCSB here seems required, as there may 
be pending GCS writes. Makes sense.

Question:
You state that we do _not_ use GCS in the hypervisor, nor in the host.
I understand that we GCSB() when we exit the vcpu context, but why would we 
need to GCSB() before getting back in?

If cpus will GCSB() on guest_exit, and host/hyp does not use GCS, there 
should be no GCS pending operation at the entry point.

Am I missing something?

Thanks!
Leo