On 03.02.26 11:08, Thomas Gleixner wrote:

On Mon, Feb 02 2026 at 17:48, Alexander Graf wrote:

quoted

To implement an HPET based NMI watchdog, the HPET code will need to
reconfigure an IOAPIC pin to NMI mode. Add a function that allows driver
code to configure an IOAPIC pin for NMI delivery mode.

A function which violates all layering of the interrupt hierarchy...

Yes, just like the device itself :). The HPET is magical.

Let me try and see whether I can just make the HPET logic require MSI 
(FSB) mode, so it can generate the NMI MSI message itself and post it 
without going through the IOAPIC in the first place. That's probably 
cleaner, more self contained and hence creates less layering violations 
and complexity in the long run.

quoted

+/**
+ * ioapic_set_nmi - Configure an IOAPIC pin for NMI delivery
+ * @gsi: Global System Interrupt number
+ * @broadcast: true to broadcast to all CPUs, false to send to CPU 0 only
+ *
+ * Configures the specified GSI for NMI delivery mode.
+ *
+ * Returns 0 on success, negative error code on failure.
+ */
+int ioapic_set_nmi(u32 gsi, bool broadcast)
+{
+     struct IO_APIC_route_entry entry = { };
+     int ioapic_idx, pin;
+
+     ioapic_idx = mp_find_ioapic(gsi);
+     if (ioapic_idx < 0)
+             return -ENODEV;
+
+     pin = mp_find_ioapic_pin(ioapic_idx, gsi);
+     if (pin < 0)
+             return -ENODEV;
+
+     entry.delivery_mode = APIC_DELIVERY_MODE_NMI;
+     entry.destid_0_7 = broadcast ? 0xFF : boot_cpu_physical_apicid;
+     entry.dest_mode_logical = 0;
+     entry.masked = 0;
+
+     ioapic_write_entry(ioapic_idx, pin, entry);

Q: How is that supposed to work with interrupt remapping?
A: Not at all.

... and yes, hopefully also gets us support for INTR if I manage to find 
the right abstraction.

Thanks a lot for the review!


Alex




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