On Thu, 11 Jul 2024, Jiaxun Yang wrote:

quoted

quoted

that's just one case, what about NaN2008 binaries on a legacy MIPS CPU ?

 It would be good to check with hard-float QEMU configured for writable 
FCSR.NAN2008 (which is one way original code was verified) that things 
have not regressed.  And also what happens if once our emulation has 
triggered for the unsupported FCSR.NAN2008 mode, an attempt is made to 
flip the mode bit via ptrace(2), e.g. under GDB, which I reckon our 
emulation permits for non-legacy CPUs (and which I think should not be 
allowed under the new setting).

PTrace is working as expected (reflects emulated value).

 Yes, sure for reads, but how about *writing* to the bit?

The actual switchable NaN hardware (M5150, P5600) uses a dedicated Config7
bit rather than writable FCSR.NAN2008 to control NaN2008 mode. This is undocumented
and not present on some RTL releases. FCSR.NAN2008 is R/O as per The MIPS32 Instruction
Set Manual. This renders the purposed test pointless.

 Yes, for R6 and arguably R5, but not for R3.  Architecture specification 
revisions 3.50 through 5.02 define FCSR.NAN2008 (and also FCSR.ABS2008) as 
either R/O or R/W, at the implementer's discretion, so it is a conforming 
implementation to have these bits writable and our FPU emulator reflects 
it.  I won't go into the details here as to why the later revisions of the 
specification have been restricted to the R/O implementation only.

 NB architecture specification revisions 3.50 through 5.01 also have the 
FCSR.MAC2008 bit defined, removed altogether later on.

  Maciej