On Mon, Jun 10, 2024 at 06:49:30PM +0100, Jessica Clarke wrote:

On 10 Jun 2024, at 05:45, Charlie Jenkins [off-list ref] wrote:

quoted

The D1/D1s SoCs support xtheadvector so it can be included in the
devicetree. Also include vlenb for the cpu.

Signed-off-by: Charlie Jenkins <redacted>
---
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 64c3c2e6cbe0..50c9f4ec8a7f 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi

@@ -27,7 +27,8 @@ cpu0: cpu@0 {

riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-       "zifencei", "zihpm";
+       "zifencei", "zihpm", "xtheadvector";
+ riscv,vlenb = <128>;

thread,vlenb

Oh right, thank you!

- Charlie

Jess

quoted

#cooling-cells = <2>;

cpu0_intc: interrupt-controller {

-- 
2.44.0


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