RE: [PATCH v1] fpga: dfl: check feature type before parse irq info
From: Wu, Hao <hidden>
Date: 2022-02-28 11:14:46
Also in:
linux-fpga, lkml
Subject: [PATCH v1] fpga: dfl: check feature type before parse irq info
From: Tianfei Zhang <redacted>
The feature ID of "Port User Interrupt" and the
"PMCI Subsystem" are identical, 0x12, but one is for FME,
other is for Port. It should check the feature type While
parsing the irq info in parse_feature_irqs().
Fixes: 8d021039cbb5 ("fpga: dfl: parse interrupt info for feature devices on
enumeration")Actually this is not a real bug, as in original design, there is no overlap for FME and Port features. This is why you see features for Port doesn't start from 0. But anyway I am good with such extension.
quoted hunk ↗ jump to hunk
Link: https://lore.kernel.org/linux- fpga/BN9PR11MB54833D7636348D62F931526CE33A9@BN9PR11MB5483.nam prd11.prod.outlook.com/ Signed-off-by: Tianfei Zhang <redacted> --- Documentation/fpga/dfl.rst | 5 +++++ drivers/fpga/dfl.c | 38 ++++++++++++++++++++++---------------- 2 files changed, 27 insertions(+), 16 deletions(-)diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ef9eec71f6f3..9ce418da1876 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst@@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driverwith matched feature id. FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +Individual DFL drivers are bound DFL devices based on Feature Type and Feature ID. +The definition of Feature Type and Feature ID can be found: + +https://github.com/OPAE/linux-dfl-feature-id/blob/master/dfl-feature-ids.rst
Thanks for tracking ID allocations. could we also add some description that if user want to implement a new private feature, then they need to submit new ID application to https://github.com/OPAE/linux-dfl-feature-id, and add some README file to guide people for the application process? Thanks Hao
quoted hunk ↗ jump to hunk
+ Location of DFLs on a PCI Device ================================ The original method for finding a DFL on a PCI device assumed the start of thediff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 599bb21d86af..6bff39ff21a0 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c@@ -940,9 +940,12 @@ static int parse_feature_irqs(structbuild_feature_devs_info *binfo, { void __iomem *base = binfo->ioaddr + ofst; unsigned int i, ibase, inr = 0; + enum dfl_id_type type; int virq; u64 v; + type = feature_dev_id_type(binfo->feature_dev); + /* * Ideally DFL framework should only read info from DFL header, but * current version DFL only provides mmio resources information for@@ -957,22 +960,25 @@ static int parse_feature_irqs(structbuild_feature_devs_info *binfo, * code will be added. But in order to be compatible to old version * DFL, the driver may still fall back to these quirks. */ - switch (fid) { - case PORT_FEATURE_ID_UINT: - v = readq(base + PORT_UINT_CAP); - ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); - inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); - break; - case PORT_FEATURE_ID_ERROR: - v = readq(base + PORT_ERROR_CAP); - ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); - break; - case FME_FEATURE_ID_GLOBAL_ERR: - v = readq(base + FME_ERROR_CAP); - ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); - break; + if (type == PORT_ID) { + switch (fid) { + case PORT_FEATURE_ID_UINT: + v = readq(base + PORT_UINT_CAP); + ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); + inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); + break; + case PORT_FEATURE_ID_ERROR: + v = readq(base + PORT_ERROR_CAP); + ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); + break; + } + } else if (type == FME_ID) { + if (fid == FME_FEATURE_ID_GLOBAL_ERR) { + v = readq(base + FME_ERROR_CAP); + ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); + } } if (!inr) { -- 2.26.2