On Tue, Feb 08, 2022 at 01:18:51AM -0700, Yu Zhao wrote:

Some architectures automatically set the accessed bit in PTEs, e.g.,
x86 and arm64 v8.2. On architectures that don't have this capability,
clearing the accessed bit in a PTE usually triggers a page fault
following the TLB miss of this PTE (to emulate the accessed bit).

Being aware of this capability can help make better decisions, e.g.,
whether to spread the work out over a period of time to reduce bursty
page faults when trying to clear the accessed bit in many PTEs.

Note that theoretically this capability can be unreliable, e.g.,
hotplugged CPUs might be different from builtin ones. Therefore it
shouldn't be used in architecture-independent code that involves
correctness, e.g., to determine whether TLB flushes are required (in
combination with the accessed bit).

Signed-off-by: Yu Zhao <redacted>
Acked-by: Brian Geffon <redacted>
Acked-by: Jan Alexander Steffens (heftig) <redacted>
Acked-by: Oleksandr Natalenko <redacted>
Acked-by: Steven Barrett <redacted>
Acked-by: Suleiman Souhlal <redacted>
Tested-by: Daniel Byrne <redacted>
Tested-by: Donald Carr <redacted>
Tested-by: Holger Hoffstätte <redacted>
Tested-by: Konstantin Kharlamov <redacted>
Tested-by: Shuang Zhai <redacted>
Tested-by: Sofia Trinh <redacted>
---
 arch/arm64/include/asm/pgtable.h | 14 ++------------
 arch/x86/include/asm/pgtable.h   |  6 +++---
 include/linux/pgtable.h          | 13 +++++++++++++
 mm/memory.c                      | 14 +-------------
 4 files changed, 19 insertions(+), 28 deletions(-)

For the arm64 bit:

Acked-by: Will Deacon <will@kernel.org>

Will