On 3/17/2021 2:18 AM, Ingo Molnar wrote:

* Yu, Yu-cheng [off-list ref] wrote:

quoted

On 3/16/2021 2:15 PM, Peter Zijlstra wrote:

quoted

On Tue, Mar 16, 2021 at 08:10:26AM -0700, Yu-cheng Yu wrote:

quoted

Control-flow Enforcement (CET) is a new Intel processor feature that blocks
return/jump-oriented programming attacks.  Details are in "Intel 64 and
IA-32 Architectures Software Developer's Manual" [1].

CET can protect applications and the kernel.  This series enables only
application-level protection, and has three parts:

    - Shadow stack [2],
    - Indirect branch tracking [3], and
    - Selftests [4].

CET is marketing; afaict SS and IBT are 100% independent and there's no
reason what so ever to have them share any code, let alone a Kconfig
knob.

We used to have shadow stack and ibt under separate Kconfig options, but in
a few places they actually share same code path, such as the XSAVES
supervisor states and ELF header for example.  Anyways I will be happy to
make changes again if there is agreement.

I was look at:

   x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states

didn't see any IBT logic - it's essentially all shadow stack state.

Which is not surprising, forward call edge integrity protection (IBT)
requires very little state, does it?

With IBT there's no nesting, no stack - the IBT state machine
basically requires the next instruction to be and ENDBR instruction,
and that's essentially it, right?

Thanks,

	Ingo

Yes, that is it.  The CET_WAIT_ENDBR bit is the status of IBT state 
machine.  There are a few bits in MSR_IA32_U_CET controlling how IBT 
works, but those are not status.

Yu-cheng