On 10/03/2021 00.48, Rob Herring wrote:

On Mon, Mar 8, 2021 at 2:56 PM Arnd Bergmann [off-list ref] wrote:

quoted

On Mon, Mar 8, 2021 at 10:14 PM Rob Herring [off-list ref] wrote:

quoted

On Mon, Mar 08, 2021 at 09:29:54PM +0100, Arnd Bergmann wrote:

quoted

On Mon, Mar 8, 2021 at 4:56 PM Rob Herring [off-list ref] wrote:

Let's just stick with 'nonposted-mmio', but drop 'posted-mmio'. I'd
rather know if and when we need 'posted-mmio'. It does need to be added
to the DT spec[1] and schema[2] though (GH PRs are fine for both).

I think the reason for having "posted-mmio" is that you cannot properly
define the PCI host controller nodes on the M1 without that: Since
nonposted-mmio applies to all child nodes, this would mean the PCI
memory space gets declared as nonposted by the DT, but the hardware
requires it to be mapped as posted.

I don't think so. PCI devices wouldn't use any of the code paths in
this patch. They would map their memory space with plain ioremap()
which is posted.

My main concern here is that this creates an inconsistency in the device 
tree representation that only works because PCI drivers happen not to 
use these code paths. Logically, having "nonposted-mmio" above the PCI 
controller would imply that it applies to that bus too. Sure, it doesn't 
matter for Linux since it is ignored, but this creates an implicit 
exception that PCI buses always use posted modes.

Then if a device comes along that due to some twisted fabric logic needs 
nonposted nGnRnE mappings for PCIe (even though the actual PCIe ops will 
end up posted at the bus anyway)... how do we represent that? Declare 
that another "nonposted-mmio" on the PCIe bus means "no, really, use 
nonposted mmio for this"?

-- 
Hector Martin (marcan@marcan.st)
Public Key: https://mrcn.st/pub