[PATCH v3 4/5] arm64: dts: exynos: Add initial support for Exynos5515 SoC
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WARM2d
From: Aiden Isik via B4 Relay <devnull+aidenisik.member.fsf.org@kernel.org>
Date: 2026-10-30 20:34:13
Also in:
b4-sent, linux-arm-kernel, linux-samsung-soc, lkml
Subsystem:
arm/samsung s3c, s5p and exynos arm architectures, the rest · Maintainers:
Krzysztof Kozlowski, Peter Griffin, Linus Torvalds
Revision v3 (2 revisions archived).
Revisions (2)
- v2
- v3 current [diff against previous]
From: Aiden Isik <redacted>
The Exynos5515 is an ARMv8 wearable SoC, used in the following devices:
- Samsung Galaxy Watch 4 (SM-R860/SM-R865/SM-R870/SM-R875)
- Samsung Galaxy Watch 4 Classic (SM-R880/SM-R885/SM-R890/SM-R895)
- Samsung Galaxy Watch FE (SM-R861/SM-R866)
- Samsung Galaxy Watch 5 (SM-R900/SM-R905/SM-R910/SM-R915)
- Samsung Galaxy Watch 5 Pro (SM-R920/SM-R925)
- Samsung Galaxy Watch 6 (SM-R930/SM-R935/SM-R940/SM-R945)
- Samsung Galaxy Watch 6 Classic (SM-R950/SM-R955/SM-R960/SM-R965)
Add the following support for this SoC:
- Both Cortex-A55 cores
- ChipID
- Generic timer
- CMU_TOP, CMU_PERI, and CMU_FSYS clock management units
The devices using this SoC suffer from the same issue as many other
Samsung devices, where the stock bootloader does not configure CNTFRQ_EL0.
To mitigate this, the correct frequency is hardcoded in the timer node.
The VGIC maintenance interrupt on this SoC is also unavailable.
Signed-off-by: Aiden Isik <redacted>
---
arch/arm64/boot/dts/exynos/exynos5515.dtsi | 178 +++++++++++++++++++++++++++++
1 file changed, 178 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5515.dtsi b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
new file mode 100644
index 000000000000..ea70a45bfa50
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5515.dtsi@@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Samsung Exynos 5515 SoC device tree source + * + * Copyright (c) 2026 Aiden Isik <aidenisik+git@member.fsf.org> + */ + +#include <dt-bindings/clock/samsung,exynos5515-cmu.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "samsung,exynos5515"; + #address-cells = <2>; + interrupt-parent = <&gic>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + }; + }; + + oscclk: osc-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "oscclk"; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupt-affinity = <&cpu0>, + <&cpu1>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x20000000>; + + #address-cells = <1>; + #size-cells = <1>; + + chipid@10000000 { + compatible = "samsung,exynos5515-chipid", + "samsung,exynos850-chipid"; + reg = <0x10000000 0x100>; + }; + + sysreg_peri: syscon@10020000 { + compatible = "samsung,exynos5515-peri-sysreg", "syscon"; + reg = <0x10020000 0x10000>; + clocks = <&cmu_peri CLK_GOUT_PERI_SYSREG_PCLK>; + }; + + cmu_peri: clock-controller@10030000 { + compatible = "samsung,exynos5515-cmu-peri"; + reg = <0x10030000 0x10000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERI_BUS>, + <&cmu_top CLK_DOUT_CMU_PERI_IP>, + <&cmu_top CLK_DOUT_CMU_PERI_UART>; + clock-names = "oscclk", + "bus", + "ip", + "uart"; + samsung,sysreg = <&sysreg_peri>; + }; + + cmu_fsys: clock-controller@10400000 { + compatible = "samsung,exynos5515-cmu-fsys"; + reg = <0x10400000 0x10000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS_MMC_CARD>, + <&cmu_top CLK_DOUT_CMU_FSYS_MMC_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS_USB20DRD>; + clock-names = "oscclk", + "bus", + "mmc_card", + "mmc_embd", + "usb20drd"; + samsung,sysreg = <&sysreg_fsys>; + }; + + sysreg_fsys: syscon@10420000 { + compatible = "samsung,exynos5515-fsys-sysreg", "syscon"; + reg = <0x10420000 0x10000>; + clocks = <&cmu_fsys CLK_GOUT_FSYS_SYSREG_PCLK>; + }; + + pmu_system_controller: system-controller@12860000 { + compatible = "samsung,exynos5515-pmu", + "samsung,exynos7-pmu", + "syscon"; + reg = <0x12860000 0x10000>; + }; + + cmu_top: clock-controller@15410000 { + compatible = "samsung,exynos5515-cmu-top"; + reg = <0x15410000 0x10000>; + #clock-cells = <1>; + clocks = <&oscclk>; + clock-names = "oscclk"; + samsung,sysreg = <&sysreg_top>; + }; + + sysreg_top: syscon@15430000 { + compatible = "samsung,exynos5515-top-sysreg", "syscon"; + reg = <0x15430000 0x10000>; + }; + + gic: interrupt-controller@15601000 { + compatible = "arm,gic-400"; + reg = <0x15601000 0x1000>, + <0x15602000 0x2000>, + <0x15604000 0x2000>, + <0x15606000 0x2000>; + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + /* VGIC maintenance interrupt is not available */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + /* + * Non-updatable, broken stock Samsung bootloader does not + * configure CNTFRQ_EL0 + */ + clock-frequency = <26000000>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 12 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; + +#include "arm/samsung/exynos-syscon-restart.dtsi"
--
2.54.0