Re: [net-next,PATCH 2/2] enetc: Make eMDIO MDC rate configurable from DT

Hi Wei,

On Tue, Oct 20, 2026 at 10:43:12AM +0300, Wei Fang wrote:

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For ENETC device, we already have a 'ref' clock in the enetc node, so
devm_clk_get(dev, NULL) may get the 'ref' clock rather than the system
clock of NETC.

Shouldn't the clock be described in the MDIO DT node ?

The enetc_mdio_read_* and enetc_mdio_write_* interfaces are not only
used by EMDIO devices, the ENETCs and NETC switches also use them.
NETC switches and ENETCs can access external PHYs or internal PCS/Serdes
through their own port MDIO registers, instead of through EMDIO devices.

Your first patch only modified the EMDIO binding-doc, not the ENETC and
switch binding-doc.

So I need to patch also
Documentation/devicetree/bindings/net/dsa/mscc,ocelot.yaml ? Any other
binding document ?

fsl,enetc.yaml and nxp,netc-switch.yaml.

However, once again, I don't highly recommend adding a clocks property to
the DTS to obtain the MDC source clock frequency. My reasons are as follows:

1. The MDC source clock is the NETC system clock, which is a fixed configuration
with a fixed frequency for each SoC, hardcode the rate in driver is simpler.

In the RCW project (https://github.com/nxp-qoriq/rcw), we have for LS1028A:
- R_SQPP_0x85bb/rcw_800_sdboot.rcw and R_SQPP_0x85bb/rcw_800_emmcboot.rcw:
  set CGA_PLL2_RAT=8, giving 800 / 3 = 266.67 MHz.
- R_SQPP_0x85bb/rcw_1500_gpu700.rcw: sets CGA_PLL2_RAT=14, giving 1400 / 3 =
  466.67 MHz.

Apart from these, yes, the other RCWs do set CGA_PLL2_RAT=12, giving 400 MHz.
But the statement in general is false.