[PATCH v3 1/3] dt-bindings: edac: cdns,ddr-edac: add Cadence DDR EDAC binding
flat view
COOLING13d
From: Paul Louvel <hidden>
Date: 2026-09-24 14:13:14
Also in:
linux-edac, linux-renesas-soc, lkml
Subsystem:
open firmware and flattened device tree bindings, the rest · Maintainers:
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Add the Cadence EDAC DT binding. Signed-off-by: Paul Louvel (Schneider Electric) <redacted> --- .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 62 ++++++++++++++++++++++ MAINTAINERS | 6 +++ 2 files changed, 68 insertions(+)
diff --git a/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
new file mode 100644
index 000000000000..e0deeb3dfb81
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml@@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/cdns,ddr-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DDR EDAC + +maintainers: + - Paul Louvel <paul.louvel@bootlin.com> + +description: > + The Cadence DDR supports DDR2 and DDR3 memory with or without ECC. + The bootloader must configure ECC mode in the memory controller. + + The memory controller supports SECDED (single bit error correction, double bit + error detection). ECC scrubbing has to be done via software. + +properties: + compatible: + items: + - const: renesas,r9a06g032-ddr-edac # RZ/N1D + - const: renesas,rzn1-ddr-edac # RZ/N1 + - const: cdns,ddr-edac + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DDR controller clock + - description: APB internal bus clock + + clock-names: + items: + - const: ddrc + - const: pclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + + edac: memory-controller@4000d000 { + compatible = "renesas,r9a06g032-ddr-edac", "renesas,rzn1-ddr-edac", "cdns,ddr-edac"; + reg = <0x4000d000 0x1000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_CLK_DDRC>, <&sysctrl R9A06G032_HCLK_DDRC>; + clock-names = "ddrc", "pclk"; + };
diff --git a/MAINTAINERS b/MAINTAINERS
index 3a19da74d00c..60db3734df5b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS@@ -5760,6 +5760,12 @@ L: linux-mm@kvack.org S: Maintained F: tools/testing/selftests/cachestat/test_cachestat.c +CADENCE DDR EDAC DRIVER +M: Paul Louvel <paul.louvel@bootlin.com> +L: linux-edac@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml + CADENCE MIPI-CSI2 BRIDGES M: Maxime Ripard <mripard@kernel.org> L: linux-media@vger.kernel.org
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2.55.0