Re: [PATCH v8 01/11] riscv: Add B to hwcap and hwprobe

From: Andrew Jones <redacted>

Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs
are all set. Also expose B via hwprobe (RISCV_HWPROBE_EXT_B in
RISCV_HWPROBE_KEY_IMA_EXT_1) so that userspace can probe B directly,
mirroring the F/D/C/V pattern where each is reported via both hwcap
and hwprobe.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Andrew Jones <redacted>
[Add B to hwprobe]
Signed-off-by: Guodong Xu <redacted>
---
v8: No change.
v7: No change.
v6: Rebase onto riscv/for-next: define RISCV_HWPROBE_EXT_B in the
     _BITULL() style of commit 8da45c93dfa9.
v5: Collected Reviewed-by from Conor Dooley.
v4: No change.
v3:
- Indent the added hwprobe.rst entry to match the normalized style.
- Rebased onto v7.1-rc6: index isa2hwcap[] via RISCV_ISA_EXT_B to match the
   macro-ization in commit 41337097f2823.
v2:
- Rebased to v7.1-rc2
- Add B to hwprobe (RISCV_HWPROBE_EXT_B at IMA_EXT_1 bit 6) and
   document it in hwprobe.rst, so userspace can probe B directly.
---
  Documentation/arch/riscv/hwprobe.rst  | 4 ++++
  arch/riscv/include/asm/hwcap.h        | 1 +
  arch/riscv/include/uapi/asm/hwcap.h   | 1 +
  arch/riscv/include/uapi/asm/hwprobe.h | 1 +
  arch/riscv/kernel/cpufeature.c        | 8 ++++++++
  arch/riscv/kernel/sys_hwprobe.c       | 1 +
  6 files changed, 16 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index bb1e0cbab36f0..69a3fc0a29b71 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst

@@ -423,3 +423,7 @@ * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional
    * :c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported,
      as defined in the RISC-V Profiles specification starting from commit
      b1d80660 ("Updated to ratified state.")
+
+  * :c:macro:`RISCV_HWPROBE_EXT_B`: The B extension is supported, as defined
+    in version 1.0 of the Bit-Manipulation ISA extensions, and implies the
+    presence of the Zba, Zbb, and Zbs sub-extensions.

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index f8db798b2654b..6a693210b2519 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h

@@ -11,6 +11,7 @@
  #include <uapi/asm/hwcap.h>
  
  #define RISCV_ISA_EXT_A		('a' - 'a')
+#define RISCV_ISA_EXT_B		('b' - 'a')
  #define RISCV_ISA_EXT_C		('c' - 'a')
  #define RISCV_ISA_EXT_D		('d' - 'a')
  #define RISCV_ISA_EXT_F		('f' - 'a')

diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
index c52bb7bbbabe9..96b7cf854e090 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h

@@ -21,6 +21,7 @@
  #define COMPAT_HWCAP_ISA_F	(1 << ('F' - 'A'))
  #define COMPAT_HWCAP_ISA_D	(1 << ('D' - 'A'))
  #define COMPAT_HWCAP_ISA_C	(1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_B	(1 << ('B' - 'A'))
  #define COMPAT_HWCAP_ISA_V	(1 << ('V' - 'A'))
  
  #endif /* _UAPI_ASM_RISCV_HWCAP_H */

diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index e6a394fbe7fce..9323feb7c3c81 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h

@@ -122,6 +122,7 @@ struct riscv_hwprobe {
  #define		RISCV_HWPROBE_EXT_ZICCIF	_BITULL(3)
  #define		RISCV_HWPROBE_EXT_ZICCRSE	_BITULL(4)
  #define		RISCV_HWPROBE_EXT_ZA64RS	_BITULL(5)
+#define		RISCV_HWPROBE_EXT_B		_BITULL(6)
  
  /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
  

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 61d21f7148305..beb766420b5bc 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c

@@ -484,6 +484,12 @@ static const unsigned int riscv_c_exts[] = {
  	RISCV_ISA_EXT_ZCD,
  };
  
+static const unsigned int riscv_b_exts[] = {
+	RISCV_ISA_EXT_ZBA,
+	RISCV_ISA_EXT_ZBB,
+	RISCV_ISA_EXT_ZBS,
+};
+
  /*
   * The canonical order of ISA extension names in the ISA string is defined in
   * Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA

@@ -532,6 +538,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
  	__RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_D, riscv_ext_d_validate),
  	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_Q),
  	__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_C, riscv_c_exts),
+	__RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B, riscv_b_exts),

  	__RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_V, riscv_v_exts,
  					  riscv_ext_vector_float_validate),
  	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_H),

@@ -1161,6 +1168,7 @@ void __init riscv_fill_hwcap(void)
  	isa2hwcap[RISCV_ISA_EXT_F] = COMPAT_HWCAP_ISA_F;
  	isa2hwcap[RISCV_ISA_EXT_D] = COMPAT_HWCAP_ISA_D;
  	isa2hwcap[RISCV_ISA_EXT_C] = COMPAT_HWCAP_ISA_C;
+	isa2hwcap[RISCV_ISA_EXT_B] = COMPAT_HWCAP_ISA_B;
  	isa2hwcap[RISCV_ISA_EXT_V] = COMPAT_HWCAP_ISA_V;
  
  	if (!acpi_disabled) {

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 7818e1d32622d..c03c6e08dd4d0 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c

@@ -207,6 +207,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
  		EXT_KEY(isainfo->isa, ZICCIF, pair->value, missing);
  		EXT_KEY(isainfo->isa, ZICCRSE, pair->value, missing);
  		EXT_KEY(isainfo->isa, ZA64RS, pair->value, missing);
+		EXT_KEY(isainfo->isa, B, pair->value, missing);
  	}
  
  	/* Now turn off reporting features if any CPU is missing it. */