[PATCH v6 5/5] arm64: dts: allwinner: sun55i: add thermal sensors
flat view
COOLING13d
From: Mikhail Kalashnikov <hidden>
Date: 2026-09-13 14:57:19
Also in:
linux-arm-kernel, linux-pm, linux-sunxi, lkml
Subsystem:
arm/allwinner sunxi soc support, the rest · Maintainers:
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Linus Torvalds
Revision v6 of 5 in this series.
Revisions (5)
From: Mikhail Kalashnikov <redacted> The A523 processor has two temperature controllers, THS0 and THS1. THS0 has only one temperature sensor, which is located in the DRAM controller. THS1 does have 4 sensors: ths1_0 - "big" cores ths1_1 - "little" cores ths1_2 - gpu ths1_3 - npu Add the thermal sensor configuration and the thermal zones. Trips temperature, polling-delay and sustainable-power parameters are derived from the manufacturer's BSP. Signed-off-by: Mikhail Kalashnikov <redacted> --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 85ef492ff..ced544154 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi@@ -11,6 +11,7 @@ #include <dt-bindings/reset/sun55i-a523-r-ccu.h> #include <dt-bindings/power/allwinner,sun55i-a523-ppu.h> #include <dt-bindings/power/allwinner,sun55i-a523-pck-600.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>;
@@ -26,6 +27,7 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0x000>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu1: cpu@100 {
@@ -33,6 +35,7 @@ cpu1: cpu@100 { device_type = "cpu"; reg = <0x100>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu2: cpu@200 {
@@ -40,6 +43,7 @@ cpu2: cpu@200 { device_type = "cpu"; reg = <0x200>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu3: cpu@300 {
@@ -47,6 +51,7 @@ cpu3: cpu@300 { device_type = "cpu"; reg = <0x300>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu4: cpu@400 {
@@ -54,6 +59,7 @@ cpu4: cpu@400 { device_type = "cpu"; reg = <0x400>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu5: cpu@500 {
@@ -61,6 +67,7 @@ cpu5: cpu@500 { device_type = "cpu"; reg = <0x500>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu6: cpu@600 {
@@ -68,6 +75,7 @@ cpu6: cpu@600 { device_type = "cpu"; reg = <0x600>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu7: cpu@700 {
@@ -75,6 +83,7 @@ cpu7: cpu@700 { device_type = "cpu"; reg = <0x700>; enable-method = "psci"; + #cooling-cells = <2>; }; };
@@ -380,6 +389,30 @@ gpadc: adc@2009000 { status = "disabled"; }; + ths1: thermal-sensor@2009400 { + compatible = "allwinner,sun55i-a523-ths1"; + reg = <0x02009400 0x400>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration0>, <&ths_calibration1>; + nvmem-cell-names = "calibration", "calibration-second-part"; + #thermal-sensor-cells = <1>; + }; + + ths0: thermal-sensor@200a000 { + compatible = "allwinner,sun55i-a523-ths0"; + reg = <0x0200a000 0x400>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC0>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration0>, <&ths_calibration1>; + nvmem-cell-names = "calibration", "calibration-second-part"; + #thermal-sensor-cells = <0>; + }; + wdt: watchdog@2050000 { compatible = "allwinner,sun55i-a523-wdt"; reg = <0x2050000 0x20>;
@@ -611,6 +644,14 @@ sid: efuse@3006000 { reg = <0x03006000 0x1000>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration0: ths-calibration0@38 { + reg = <0x38 0x8>; + }; + + ths_calibration1: ths-calibration1@44 { + reg = <0x44 0x8>; + }; }; gic: interrupt-controller@3400000 {
@@ -1145,4 +1186,135 @@ npu: npu@7122000 { power-domains = <&ppu PD_NPU>; }; }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths1 1>; + sustainable-power = <1200>; + + trips { + cpu-trip-0 { + temperature = <70000>; + type = "passive"; + hysteresis = <0>; + }; + + cpu0_target: cpu-trip-1 { + temperature = <90000>; + type = "passive"; + hysteresis = <0>; + }; + + cpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths1 0>; + sustainable-power = <1600>; + + trips { + cpu-trip-0 { + temperature = <70000>; + type = "passive"; + hysteresis = <0>; + }; + + cpu4_target: cpu-trip-1 { + temperature = <90000>; + type = "passive"; + hysteresis = <0>; + }; + + cpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_target>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths1 2>; + sustainable-power = <2400>; + + trips { + gpu-trip-0 { + temperature = <60000>; + type = "passive"; + hysteresis = <0>; + }; + + gpu-trip-1 { + temperature = <90000>; + type = "passive"; + hysteresis = <0>; + }; + + gpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + npu-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths1 3>; + + trips { + npu-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths0>; + + trips { + ddr-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + }; };
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2.55.0