[PATCH v6 1/2] dt-bindings: dmaengine: Add support for ATCDMAC300 DMA engine
From: CL Wang <cl634@andestech.com>
Date: 2026-09-11 07:42:40
Also in:
dmaengine, linux-hardening, lkml
Subsystem:
dma generic offload engine subsystem, open firmware and flattened device tree bindings, the rest · Maintainers:
Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Document devicetree bindings for Andes ATCDMAC300 DMA engine
ATCDMAC300 is the IP name, which is embedded in AndesCore-based
platforms or SoCs such as AE350 and Qilai.
Signed-off-by: CL Wang <cl634@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes for v6:
- Rebase onto dmaengine/next; no changes from v5
Changes for v5:
- No changes from v4
Changes for v4:
- Use items list format with descriptions for reg property
as suggested by Conor Dooley
Changes for v3:
- Rename DT binding file from andestech,qilai-dma.yaml to
andestech,ae350-dma.yaml.
- Deprecate IP-core-based compatible usage and align with
SoC/platform-based strings.
- Dropped Acked-by tag from Conor Dooley due to the above change.
---
.../bindings/dma/andestech,ae350-dma.yaml | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/andestech,ae350-dma.yaml
diff --git a/Documentation/devicetree/bindings/dma/andestech,ae350-dma.yaml b/Documentation/devicetree/bindings/dma/andestech,ae350-dma.yaml
new file mode 100644
index 000000000000..f040a2bf7d4b
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/andestech,ae350-dma.yaml@@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/andestech,ae350-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes ATCDMAC300 DMA Controller + +maintainers: + - CL Wang <cl634@andestech.com> + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - andestech,qilai-dma + - const: andestech,ae350-dma + - const: andestech,ae350-dma + + reg: + minItems: 1 + items: + - description: DMA controller register range + - description: cache control in IOCP controller + + reg-names: + minItems: 1 + items: + - const: dma + - const: iocp + + interrupts: + maxItems: 1 + + "#dma-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dma-controller@f0c00000 { + compatible = "andestech,ae350-dma"; + reg = <0x0 0xf0c00000 0x0 0x1000>, + <0x0 0xe8000000 0x0 0x10>; + reg-names = "dma", "iocp"; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + }; + }; +...
--
2.34.1