[PATCH v8 1/2] dt-bindings: clock: add TI CDCE6214 binding
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: 2026-09-09 08:54:20
Also in:
linux-clk, linux-gpio, lkml
Subsystem:
common clk framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Add device tree binding for the CDCE6214, an Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <redacted> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- .../devicetree/bindings/clock/ti,cdce6214.yaml | 192 +++++++++++++++++++++ include/dt-bindings/clock/ti,cdce6214.h | 25 +++ 2 files changed, 217 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/ti,cdce6214.yaml b/Documentation/devicetree/bindings/clock/ti,cdce6214.yaml
new file mode 100644
index 0000000000000..4a9c9155894af
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti,cdce6214.yaml@@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,cdce6214.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI CDCE6214 programmable clock generator with PLL + +maintainers: + - Sascha Hauer <s.hauer@pengutronix.de> + +description: > + Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, + Two Inputs, and Internal EEPROM + + - CDCE6214: https://www.ti.com/product/CDCE6214 + +properties: + compatible: + enum: + - ti,cdce6214 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - enum: [ priref, secref ] + - const: secref + + '#clock-cells': + const: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^conf': + type: object + additionalProperties: false + $ref: /schemas/pinctrl/pincfg-node.yaml# + + properties: + pins: + items: + enum: [priref, secref, out0, out1, out2, out3, out4 ] + + ti,io-standard: + description: | + 1: CMOS + 2: LVDS + 3: Low-Power HCSL + 4: XTAL mode + 5: differential + enum: [1, 2, 3, 4, 5] + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,xo-cload-femtofarads: + description: Load capacity for XO in Femtofarad + + ti,xo-bias-microamp: + description: Bias current setting of the XO + + ti,cmosp-mode: + description: | + Driving mode for CMOSN output: + 1: Low Polarity + 2: High Polrity + 3: Disable + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + ti,cmosn-mode: + description: | + Driving mode for CMOSN output: + 1: Low Polarity + 2: High Polrity + 3: Disable + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + allOf: + - if: + properties: + pins: + contains: + const: priref + then: + properties: + io-standard: + enum: [ 1, 5 ] + + - if: + properties: + pins: + contains: + const: secref + then: + properties: + io-standard: + enum: [ 1, 4, 5 ] + + - if: + properties: + pins: + contains: + const: out0 + then: + properties: + io-standard: + enum: [ 1 ] + + - if: + properties: + pins: + contains: + enum: + - out1 + - out4 + then: + properties: + io-standard: + enum: [ 1, 2, 3 ] + + - if: + properties: + pins: + contains: + enum: + - out2 + - out3 + then: + properties: + io-standard: + enum: [ 2, 3 ] + + required: + - pins + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/ti,cdce6214.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + clock-generator@67 { + compatible = "ti,cdce6214"; + reg = <0x67>; + #clock-cells = <1>; + clocks = <&clock_ref25m>; + clock-names = "priref"; + + cdce6214_pins: cdce6214-pins { + conf1 { + pins = "secref"; + ti,io-standard = <CDCE6214_IOSTD_XTAL>; + ti,xo-cload-femtofarads = <8100>; + ti,xo-bias-microamp = <100>; + }; + + conf2 { + pins = "out1"; + ti,io-standard = <CDCE6214_IOSTD_CMOS>; + ti,cmosp-mode = <CDCE6214_CMOS_MODE_HIGH>; + ti,cmosn-mode = <CDCE6214_CMOS_MODE_LOW>; + }; + + conf3 { + pins = "out4"; + ti,io-standard = <CDCE6214_IOSTD_CMOS>; + ti,cmosp-mode = <CDCE6214_CMOS_MODE_HIGH>; + ti,cmosn-mode = <CDCE6214_CMOS_MODE_LOW>; + }; + }; + }; + };
diff --git a/include/dt-bindings/clock/ti,cdce6214.h b/include/dt-bindings/clock/ti,cdce6214.h
new file mode 100644
index 0000000000000..41ec4f8868bbb
--- /dev/null
+++ b/include/dt-bindings/clock/ti,cdce6214.h@@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +#ifndef _DT_BINDINGS_CLK_TI_CDCE6214_H +#define _DT_BINDINGS_CLK_TI_CDCE6214_H + +/* Clock indices for the clocks provided by the CDCE6214 */ +#define CDCE6214_CLK_OUT0 2 +#define CDCE6214_CLK_OUT1 3 +#define CDCE6214_CLK_OUT2 4 +#define CDCE6214_CLK_OUT3 5 +#define CDCE6214_CLK_OUT4 6 +#define CDCE6214_CLK_PLL 7 +#define CDCE6214_CLK_PSA 8 +#define CDCE6214_CLK_PSB 9 + +#define CDCE6214_IOSTD_CMOS 1 +#define CDCE6214_IOSTD_LVDS 2 +#define CDCE6214_IOSTD_LP_HCSL 3 +#define CDCE6214_IOSTD_XTAL 4 +#define CDCE6214_IOSTD_DIFF 5 + +#define CDCE6214_CMOS_MODE_LOW 1 +#define CDCE6214_CMOS_MODE_HIGH 2 +#define CDCE6214_CMOS_MODE_DISABLED 3 + +#endif /* _DT_BINDINGS_CLK_TI_CDCE6214_H */
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2.47.3