Re: [PATCH v9 08/18] spi: cadence-quadspi: add PHY tuning support

On 08/09/2026 at 18:35:18 +0530, Santhosh Kumar K [off-list ref] wrote:

Hello Miquel,

On 03/09/26 13:46, Miquel Raynal wrote:

quoted

Hi Santhosh,

quoted

The DQS bit in CQSPI_REG_READCAPTURE is used for read data capture and
it's not consulted during writes.

In the end, how do you know you can expect a DQS signal during reads?
Will that work if the chip does not enable it? I still do not understand
how this can work.

The current implementation derives 'use_dqs' from the DTR flag in the
read_op rather than querying spi_mem_has_dqs().

For SPI NOR flashes, this works with the current SPI/MTD flow as the
device is switched to octal DTR mode before the execute_tuning() call.
The current NOR mode-switch implementations enable DTR and DQS
together, so by the time tuning callback runs, DTR on the read_op
reflects the active DTR and DQS mode. This is consistent across the
current octal-DTR NOR support.

For SPI NAND flashes, this series only supports SDR PHY mode, so DQS
is not involved in the NAND path.

The gap is that the NOR path relies on the implicit relationship
between DTR and DQS rather than tracking the DQS state through the
SPI-MEM API. I agree that checking spi_mem_has_dqs() would be the
proper approach and would also handle any future case where DTR and
DQS can be controlled independently. I'll address this gap in a
follow-up series.

Clear. Thanks for the feedback.

Miquèl