Re: [PATCH v5 2/4] arm64: dts: intel: agilex5: add USB3.1 controller node
From: sashiko-bot@kernel.org
Date: 2026-09-07 08:44:59
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] The `dma-ranges` property attempts to map a 40-bit (1 TiB) address window into a strictly 32-bit parent bus, which will break DMA addressing above 4 GiB. -- commit 37652f3fe88e1fdb5283901dda73de167a957be5 Author: Adrian Ng Ho Yin [off-list ref] arm64: dts: intel: agilex5: add USB3.1 controller node This commit adds a DTS node for the Synopsys DWC3 USB3.1 controller on the Agilex5 SoC. It places the node under a simple-bus with a 40-bit dma-ranges window to match the interconnect's USB DMA address width.
quoted hunk ↗ jump to hunk
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index f54767d1526e1..523f722a2a642 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
[ ... ]
quoted hunk ↗ jump to hunk
@@ -493,6 +493,41 @@ usb0: usb@10b00000 { status = "disabled"; }; + usb31_bus: usb-bus@11000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x11000000 0x0 0x100000>; + /* + * USB interconnect DMA is limited to 40-bit addresses + * (1 TiB window from 0). + */ + dma-ranges = <0x0 0x0 0x0 0x100 0x0>;
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [Severity: High] Does this 1 TiB DMA mapping conflict with the 32-bit parent bus? The usb31_bus node defines a 1 TiB DMA window (0x100 0x0 size) mapped into its parent node starting at address 0x0. However, the parent node appears to define #address-cells = <1>, representing a strictly 32-bit (4 GiB) address space. Since a 1 TiB mapping cannot logically fit within a 32-bit parent address space, will this truncate addresses above 4 GiB during DMA translation in of_translate_dma_address(), leading to DMA mapping errors or IOMMU faults when the USB 3.1 controller performs a DMA transaction to memory above the 4 GiB physical address boundary?
+
+ usb31: usb@0 {
+ compatible = "altr,agilex5-dwc3";[ ... ] -- Sashiko AI review · https://sashiko.dev/#/patchset/cover.1788757821.git.adrian.ho.yin.ng@altera.com?part=2