Re: [PATCH v2 13/15] phy: starfive: Add jh7110-inno-hdmi-phy driver
From: Maud Spierings <hidden>
Date: 2026-09-06 14:59:37
Also in:
dri-devel, linux-arm-kernel, linux-clk, linux-phy, linux-riscv, linux-rockchip, lkml
On 9/6/26 07:39, Dominique Belhachemi wrote:
On Sun, Aug 30, 2026 at 10:17 AM Maud Spierings
<maud_spierings@murena.io <mailto:maud_spierings@murena.io>> wrote:
I was still having some glitching happening on the display, but I've
found the way to fix that, the question is what is actually
happening here.
0x29590020 <- 0x00000005
This one I have no idea, it is 0x00000009 with this patch series but
with the vendor kernel I get the value above. When I hook up my
external
display (regular 1440p) this becomes 0x0000000D on the vendor kernel.
But I can't find this register being written to anywhere there?
Maybe this needs to be swapped?
drivers/gpu/drm/bridge/inno-hdmi.c
-#define v_HSYNC_POLARITY(n) ((n) << 3)
-#define v_VSYNC_POLARITY(n) ((n) << 2)
+#define v_HSYNC_POLARITY(n) ((n) << 2)
+#define v_VSYNC_POLARITY(n) ((n) << 3)Those seem to only be relevant the 0x08 register: > #define HDMI_VIDEO_TIMING_CTL 0x08 also in the code: > /* Set detail external video timing polarity and interlace mode */ > value = v_EXTERANL_VIDEO(1); > value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? > v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0); > value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? > v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0); > value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? > v_INETLACE(1) : v_INETLACE(0); > hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);