Re: [PATCH v6 12/27] clk: mediatek: pll: Add PLL stabilization delay definition
From: sashiko-bot@kernel.org
Date: 2026-09-04 16:11:31
Also in:
linux-clk
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] Comment retains a hardcoded delay value, defeating the purpose of the macro refactoring. -- commit ed78802d4853a74588db6e1da90538ffeb9ae7a6 Author: Louis-Alexis Eyraud [off-list ref] clk: mediatek: pll: Add PLL stabilization delay definition This commit introduces a new macro PLL_STABILIZATION_DELAY to replace hardcoded 20us delays used for PLL stabilization.
quoted hunk ↗ jump to hunk
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 2aaf2871ecf6a..9a197a657dce0 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c
[ ... ]
quoted hunk ↗ jump to hunk
@@ -306,7 +308,7 @@ static int mtk_pll_prepare_fenc_setclr(struct clk_hw *hw) writel(BIT(pll->data->pll_en_bit), pll->en_set_addr); /* Wait 20us after enable for the PLL to stabilize */
[Severity: Low] This isn't a bug, but the comment still hardcodes the 20us value that the patch abstracts. Should this comment be updated to remove the hardcoded value so it won't become stale if the PLL_STABILIZATION_DELAY macro is updated in the future?
- udelay(20); + udelay(PLL_STABILIZATION_DELAY); return 0; }
-- Sashiko AI review · https://sashiko.dev/#/patchset/20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com?part=12