[PATCH v3 1/5] dt-bindings: phy: Add CIX Sky1 USB3 PHY
From: Hongliang Yang <hidden>
Date: 2026-09-03 02:35:58
Also in:
linux-arm-kernel, linux-phy, linux-usb, lkml
Subsystem:
generic phy framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Add device tree binding for the CIX Sky1 USB3 PHY, a multi-port SuperSpeedPlus PHY supporting up to two USB3 lanes. Signed-off-by: Hongliang Yang <redacted> --- .../bindings/phy/cix,sky1-usb3-phy.yaml | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml
new file mode 100644
index 000000000000..5b025a48c844
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml@@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/cix,sky1-usb3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 USB3 PHY + +maintainers: + - Hongliang Yang <hongliang.yang@cixtech.com> + +description: + The CIX Sky1 USB3 PHY is a multi-port SuperSpeedPlus PHY that + supports up to two USB3 lanes. Each port is represented as a + child node of the PHY controller. + +properties: + compatible: + const: cix,sky1-usb3-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: APB register interface clock + - description: PHY reference clock + + clock-names: + items: + - const: apb + - const: ref + + resets: + items: + - description: PHY reset + - description: PHY APB preset + + reset-names: + items: + - const: core + - const: apb + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^usb-port@[0-9a-f]+$": + type: object + description: + A single USB3 PHY port/lane. + + properties: + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/cix,sky1.h> + #include <dt-bindings/reset/cix,sky1-s5-system-control.h> + + usb-phy@9210000 { + compatible = "cix,sky1-usb3-phy"; + reg = <0x9210000 0x40000>; + #address-cells = <1>; + clocks = <&scmi_clk CLK_TREE_USB3A_PHY3_GATE>, + <&scmi_clk CLK_TREE_USB3A_PHY_x2_REF>; + clock-names = "apb", "ref"; + resets = <&s5_syscon SKY1_USBPHY_SS_RST_N>, + <&s5_syscon SKY1_USBPHY_SS_PST_N>; + reset-names = "core", "apb"; + #size-cells = <0>; + + usb-port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + usb-port@1 { + reg = <1>; + #phy-cells = <0>; + }; + };
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2.54.0