Re: [PATCH v2 02/15] dt-bindings: display: bridge: Add starfive,jh7110-inno-hdmi-controller
flat view
From: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Date: 2026-08-28 14:12:26
Also in:
dri-devel, linux-arm-kernel, linux-clk, linux-phy, linux-riscv, linux-rockchip, lkml
在 2026-08-28五的 15:47 +0200，Michal Wilczynski写道：
quoted hunk ↗ jump to hunk
Add the dt-binding for the StarFive JH7110 Innosilicon HDMI controller (DRM bridge). This device is the second child of the starfive,jh7110-hdmi-subsystem node. It consumes register access clocks (sys, mclk, bclk) from the voutcrg and both the pixel clock (pclk) and the PHY from its hdmi_phy sibling. Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> --- .../starfive,jh7110-inno-hdmi-controller.yaml | 109 +++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/starfive,jh7110- inno-hdmi-controller.yaml b/Documentation/devicetree/bindings/display/bridge/starfive,jh7110- inno-hdmi-controller.yaml new file mode 100644 index 0000000000000000000000000000000000000000..0e584e7b756e24e2f99a62daab3 117bbf4b472b6--- /dev/null +++b/Documentation/devicetree/bindings/display/bridge/starfive,jh7110- inno-hdmi-controller.yaml@@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id:http://devicetree.org/schemas/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Innosilicon HDMI Controller + +maintainers: + - Michal Wilczynski [off-list ref] + +description: + The controller portion of the StarFive JH7110 INNO HDMI IP. + +properties: + compatible: + const: starfive,jh7110-inno-hdmi-controller + + interrupts: + maxItems: 1 + + clocks: + items: + - description: System clock for register access + - description: Module clock + - description: Bus clock + - description: Pixel clock from PHY + + clock-names: + items: + - const: sys + - const: mclk + - const: bclk + - const: pclk + + resets: + maxItems: 1 + + reset-names: + const: hdmi_tx + + phys: + maxItems: 1 + + phy-names: + const: hdmi-phy + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: + A graph node with one input port and one output port.
Maybe this device should handle the display mux in the dom_vout_syscon part. This syscon is documented in the JH7110 TRM, and the address is at 0x295b0000. According to the manual, bit 30:25 of register 0x4 and bit 4 of register 0x8 (which is marked as u2_display_panel_mux_panel_sel, but in the block diagram of display subsystem, it could be seen that the mux controlling the input of HDMI_Ctrl is u2_display_panel_mux) is related to the HDMI display, with the setup of 8-bit DPI0 connected to HDMI controller as the default value (u0_hdmi_data_mapping_dpi_dp_sel = 0 (DPI), u0_hdmi_data_mapping_dpi_bit_depth = 0 (8-bit), u2_display_panel_mux_panel_sel = 0 (Panel 0)), and this is currently your example setup. At least leave a syscon property pointing to the syscon would be then useful, and maybe it's better to setup the syscon values based on which DC8200 output interface is in use. Thanks, Icenowy
+
+required:
+ - compatible
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - phys
+ - phy-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ # Shown as a child of the HDMI subsystem node; see
+ # Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-
subsystem.yaml
+ # for the full node.
+ - |
+ #include <dt-bindings/clock/starfive,jh7110-crg.h>
+ #include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+ controller {
+ compatible = "starfive,jh7110-inno-hdmi-controller";
+ clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
+ <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
+ <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>,
+ <&hdmi_phy>;
+ clock-names = "sys", "mclk", "bclk", "pclk";
+ interrupts = <99>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+ resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
+ reset-names = "hdmi_tx";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ endpoint {
+ remote-endpoint = <&dpu_out_dpi0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+ };
+
+...