The AMD CPM6 PCIe controller is based on the Synopsys DesignWare PCIe
IP and integrates two PCIe host controller instances. Add the
"amd,versal2-cpm6-host" and "amd,versal2-cpm6-host1" compatible strings
to describe the HOST0 and HOST1 controller instances.
Add "intr" to the vendor-specific reg-names in snps,dw-pcie.yaml for
the per-controller interrupt register region used by CPM6.
Update amd,versal2-mdb-host.yaml with separate register definitions:
- MDB5: 4 regions (slcr, config, dbi, atu)
- CPM6: 5 regions (slcr, config, dbi, atu, intr)
Signed-off-by: Sai Krishna Musham <redacted>
Sashiko has reviewed this patch and found no issues. It looks great!
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Sashiko AI review · https://sashiko.dev/#/patchset/20260819172057.3636214-1-sai.krishna.musham@amd.com?part=1