[PATCH v3] riscv: dts: spacemit: k3: Add QSPI support for Pico-ITX board
From: Zhengyu He <hidden>
Date: 2026-07-11 01:39:07
Also in:
linux-riscv, lkml, spacemit
Subsystem:
risc-v architecture, risc-v spacemit soc support, the rest · Maintainers:
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yixun Lan, Linus Torvalds
Enable QSPI with proper pinmux on the Pico-ITX board, and describe the NOR flash wired to it. Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Cody Kang <redacted> Signed-off-by: Zhengyu He <redacted> --- Changes in v3: - Drop the already applied binding patch. - Update the subject and simplify the commit message. - Use the existing qspi_cfg label for the Pico-ITX pinctrl override. - Rebase onto v7.2-rc2. Changes in v2: - Add "spacemit,k1-qspi" fallback to the K3 QSPI compatible. - Reordered Signed-off-by trailers. Base: v7.2-rc2 Here is version 2: https://lore.kernel.org/all/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-0-52bce26e5fd8@gmail.com/ (local) Here is version 1: https://lore.kernel.org/r/20260519-k3-pico-itx-qspi-v1-v1-0-c32afeeaf741@gmail.com (local) --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 56 ++++++++++++++++++++++++++++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 21 +++++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 17 +++++++++ 3 files changed, 94 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
index b89c1521e664..fd2b154f275a 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts@@ -200,6 +200,62 @@ phy0: phy@1 { }; }; +&qspi_cfg { + qspi-pins { + power-source = <1800>; + }; + + qspi-cs0-pins { + power-source = <1800>; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + vcc-supply = <&aldo2>; /* PMIC_VCC1V8_QSPI */ + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootinfo@0 { + reg = <0x0 0x20000>; + }; + + fsbl@20000 { + reg = <0x20000 0x80000>; + }; + + env@a0000 { + reg = <0xa0000 0x10000>; + }; + + esos@b0000 { + reg = <0xb0000 0x100000>; + }; + + opensbi@1b0000 { + reg = <0x1b0000 0x60000>; + }; + + uboot@210000 { + reg = <0x210000 0x5f0000>; + }; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_0_cfg>;
diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
index 3ee1471f3798..846d5e8cc783 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi@@ -679,6 +679,27 @@ pwm19-2-pins { }; }; + /omit-if-no-ref/ + qspi_cfg: qspi-cfg { + qspi-pins { + pinmux = <K3_PADCONF(138, 0)>, /* qspi dat0 */ + <K3_PADCONF(139, 0)>, /* qspi dat1 */ + <K3_PADCONF(140, 0)>, /* qspi dat2 */ + <K3_PADCONF(141, 0)>, /* qspi dat3 */ + <K3_PADCONF(144, 0)>; /* qspi clk */ + + bias-disable; + drive-strength = <25>; + }; + + qspi-cs0-pins { + pinmux = <K3_PADCONF(142, 0)>; /* qspi cs0 */ + + bias-disable; + drive-strength = <25>; + }; + }; + /omit-if-no-ref/ uart0_0_cfg: uart0-0-cfg { uart0-0-pins {
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 19fc9b49668e..9a49dd8032bf 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi@@ -1099,6 +1099,23 @@ pll: clock-controller@d4090000 { #clock-cells = <1>; }; + qspi: spi@d420c000 { + compatible = "spacemit,k3-qspi", + "spacemit,k1-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xd420c000 0x0 0x1000>, + <0x0 0xb8000000 0x0 0xc00000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>, + <&syscon_apmu CLK_APMU_QSPI>; + clock-names = "qspi_en", "qspi"; + resets = <&syscon_apmu RESET_APMU_QSPI>, + <&syscon_apmu RESET_APMU_QSPI_BUS>; + interrupts = <117 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + syscon_apmu: system-controller@d4282800 { compatible = "spacemit,k3-syscon-apmu"; reg = <0x0 0xd4282800 0x0 0x400>;
--- base-commit: 8cdeaa50eae8dad34885515f62559ee83e7e8dda change-id: 20260709-k3-pico-itx-qspi-v3-7f81b2c023cc Best regards, -- Zhengyu He [off-list ref]