The RZ Smarc Crarrier-II board has PCIe slots mounted on it.
Enable PCIe support.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v9:
- Renamed gpio-hog node from 'pcie-clkreq-n' to 'pcie-clkreq-n-hog'
to satisfy DT schema naming constraint (reported by Biju)
- Updated line-name with proper signal name on the board
- Fixed node sort order within &pinctrl (reported by Geert)
v8: No changes
v7: No changes
v6: No changes
v5: No changes
v4: No changes
v3:
- Splitted enablement into common carrier dtsi and board dts
v2:
- Removed board-specific dma-ranges.
- Merged enablement and pinmux assignment in same file
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 16 ++++++++++++++++
arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 4 ++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 696903dc7a63..3e24e916874f 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -122,6 +122,11 @@ key-sleep {
#endif
};
+&pcie {
+ pinctrl-0 = <&pcie_pins>;
+ pinctrl-names = "default";
+};
+
&pinctrl {
canfd_pins: canfd {
can1_pins: can1 {@@ -145,6 +150,17 @@ nmi_pins: nmi {
input-schmitt-enable;
};
+ pcie-clkreq-n-hog {
+ gpio-hog;
+ gpios = <RZG3E_GPIO(4, 5) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "PCIE_M2B_CKREQ";
+ };
+
+ pcie_pins: pcie {
+ pinmux = <RZG3E_PORT_PINMUX(G, 7, 1)>; /* PCIE_RST_OUT# */
+ };
+
rsci2_pins: rsci2 {
pinmux = <RZG3E_PORT_PINMUX(1, 0, 1)>, /* RXD2 */
<RZG3E_PORT_PINMUX(1, 1, 1)>, /* TXD2 */diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index b607b5d6c259..e2a34577a1a1 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -96,6 +96,10 @@ &i2c0 {
clock-frequency = <400000>;
};
+&pcie {
+ status = "okay";
+};
+
&scif0 {
status = "okay";
};--
2.25.1