[RFC][PATCH 4/4] ARM: dts: renesas: r8a7740: Describe coresight on R-Mobile A1
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: 2026-03-28 00:00:56
Also in:
linux-arm-kernel, linux-clk, linux-renesas-soc, lkml
Subsystem:
arm/risc-v/renesas architecture, the rest · Maintainers:
Geert Uytterhoeven, Magnus Damm, Linus Torvalds
Describe coresight topology on R-Mobile A1. Extend the current PTM node with connection funnel, TPIU, ETB and replicator. The coresight on this hardware is clocked from the ZT/ZTR trace clock. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> --- Cc: Conor Dooley <conor+dt@kernel.org> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Rob Herring <robh@kernel.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 114 ++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi
index 0a622da79dc1a..eb1abc90c4f59 100644
--- a/arch/arm/boot/dts/renesas/r8a7740.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi@@ -18,7 +18,7 @@ / { cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0x0>;
@@ -59,9 +59,117 @@ pmu { interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; }; - ptm { - compatible = "arm,coresight-etm3x"; + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "atclk"; power-domains = <&pd_d4>; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + + in-ports { + /* replicator input port */ + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + etb@e6fa1000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0xe6fa1000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@e6fa3000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0xe6fa3000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + power-domains = <&pd_d4>; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + funnel { + compatible = "arm,coresight-static-funnel"; + + /* funnel output ports */ + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + }; + }; + + ptm@e6fbc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0xe6fbc000 0x1000>; + clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names = "apb_pclk", "atclk"; + cpu = <&cpu0>; + power-domains = <&pd_d4>; + + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; }; ceu0: ceu@fe910000 {
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2.53.0