[PATCH v3 3/3] arm64: dts: hpe: Add HPE GSC SoC and DL340 Gen12 board DTS
From: nick.hawkins@hpe.com
Date: 2026-03-27 17:45:11
Also in:
linux-arm-kernel, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
From: Nick Hawkins <nick.hawkins@hpe.com> Add SoC-level DTSI for the HPE GSC ARM64 BMC SoC, covering the CPU cluster, GIC v3 interrupt controller, ARM64 generic timer, and console UART. Add the board-level DTS for the HPE DL340 Gen12, which includes gsc.dtsi and adds memory and chosen nodes. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> --- arch/arm64/boot/dts/hpe/Makefile | 2 + arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts | 18 ++++ arch/arm64/boot/dts/hpe/gsc.dtsi | 104 +++++++++++++++++++++ 3 files changed, 124 insertions(+) create mode 100644 arch/arm64/boot/dts/hpe/Makefile create mode 100644 arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts create mode 100644 arch/arm64/boot/dts/hpe/gsc.dtsi
diff --git a/arch/arm64/boot/dts/hpe/Makefile b/arch/arm64/boot/dts/hpe/Makefile
new file mode 100644
index 000000000000..6b547b8a8154
--- /dev/null
+++ b/arch/arm64/boot/dts/hpe/Makefile@@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_HPE) += gsc-dl340gen12.dtb
diff --git a/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
new file mode 100644
index 000000000000..42cfeac99029
--- /dev/null
+++ b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts@@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "gsc.dtsi" + +/ { + compatible = "hpe,gsc-dl340gen12", "hpe,gsc"; + model = "HPE ProLiant DL340 Gen12"; + + chosen { + stdout-path = &uartc; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; +};
diff --git a/arch/arm64/boot/dts/hpe/gsc.dtsi b/arch/arm64/boot/dts/hpe/gsc.dtsi
new file mode 100644
index 000000000000..087688b089e9
--- /dev/null
+++ b/arch/arm64/boot/dts/hpe/gsc.dtsi@@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HPE GSC + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0xa0008048>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0xa0008048>; + }; + }; + + osc: clock-33333333 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc"; + clock-frequency = <33333333>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gic>; + }; + + soc: soc@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x80000000>; + ranges; + + gic: gic@ce000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + redistributor-stride = <0x0 0x20000>; + #redistributor-regions = <1>; + reg = <0xce000000 0x10000>, + <0xce060000 0x40000>, + <0xce200000 0x40000>; + }; + + uarta: serial@c00000e0 { + compatible = "ns16550a"; + reg = <0xc00000e0 0x8>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + uartb: serial@c00000e8 { + compatible = "ns16550a"; + reg = <0xc00000e8 0x8>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + uartc: serial@c00000f0 { + compatible = "ns16550a"; + reg = <0xc00000f0 0x8>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + uarte: serial@c00003e0 { + compatible = "ns16550a"; + reg = <0xc00003e0 0x8>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + }; +};
--
2.34.1