On Wed, 29 Oct 2025 18:37:29 +0530, Ravi Patel wrote:
Add below clock PLL support for Axis ARTPEC-9 SoC platform:
- pll_a9fracm: Integer PLL with mid frequency FVCO (800 to 6400 MHz)
This is used in ARTPEC-9 SoC for shared PLL
- pll_a9fraco: Integer/Fractional PLL with mid frequency FVCO
(600 to 2400 MHz)
This is used in ARTPEC-9 SoC for Audio PLL
[...]
Applied, thanks!
[2/4] clk: samsung: Add clock PLL support for ARTPEC-9 SoC
https://git.kernel.org/krzk/linux/c/f051dc5bc8e785b221d2e69094e774507c3a52dd
Best regards,
--
Krzysztof Kozlowski [off-list ref]