Hi Xuyang Dong

On Thu, 2026-02-05 at 17:33 +0800, dongxuyang@eswincomputing.com wrote:

From: Xuyang Dong <dongxuyang@eswincomputing.com>

Thank you very much!

For the whole series.

Tested-by: Marcel Ziswiler <redacted> # ebc77

BTW: Should anybody else want to easily test mainline on EBC77 [1].

[1] https://github.com/riscv/meta-riscv/pull/594

Cheers

Marcel

The link [1] provides the official documentation for the EIC7700. Section 3.2
covers the clock subsystem.

[1] https://www.sifive.com/document-file/eic7700x-datasheet

Updates:
  Changes in v10:
  - Updated driver file
    - Add a private clock divider API named 'eswin_register_clkdiv' to
      register divider clocks with private flag.
      Define 'ESWIN_PRIV_DIV_MIN_2' private flag for registering the clock
      dividers whose division ratio start from 2.
      Implement the private set_rate, recalc_rate, and determine_rate accordingly.
    - Add CLK_DIVIDER_ALLOW_ZERO flag to the clock dividers whose division
      ratio start from 0.
    - Replace CONFIG_ARCH_ESWIN with CONFIG_COMMON_CLK_ESWIN in the Makefile.
    - Modify the help description of COMMON_CLK_EIC7700.
    - Move register offset definitions from 'clk-eic7700.h' to 'clk-eic7700.c' and
      remove the 'clk-eic7700.h'. Remove '_CTRL' from the offset names.
    - Remove all unused headers.
    - Use devm_platform_ioremap_resource() instead of devm_of_iomap().
    - Export the functions from clk.c as symbols.
    - Use readl_poll_timeout().
    - Use 'clk_parent_data' and '.hw' instead of string parent names.
    - Rename the header file from clk.h to common.h.
    - Rename macros from EIC7700_* to ESWIN_* in common.h.
    - Add a new function, 'eswin_clk_register_clks', which can register
      divider, mux, gate, and fixed-factor clocks based on their types.
    - Add structure 'eswin_clk_info' to manage the clocks that need to be registered
      in a specific order.
    - Add macros 'ESWIN_*_TYPE' to define divider, mux, gate, and fixed-factor clocks
      with type. Add enum 'eswin_clk_type' for these types.
    - Remove 'eswin_clk_register_mux_tbl'. Use 'eswin_clk_register_mux' to register
      mux clocks with or without table.
    - Add xtal24m as the parent clock of the PLL.
    - Change 2025 to 2026 in all files.

  - Link to v9: https://lore.kernel.org/all/20251229105844.1089-1-dongxuyang@eswincomputing.com/ (local)

[snip]

Xuyang Dong (3):
  dt-bindings: clock: eswin: Documentation for eic7700 SoC
  clock: eswin: Add eic7700 clock driver
  MAINTAINERS: Add entry for ESWIN EIC7700 clock driver

 .../bindings/clock/eswin,eic7700-clock.yaml   |   46 +
 MAINTAINERS                                   |    8 +
 drivers/clk/Kconfig                           |    1 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/eswin/Kconfig                     |   15 +
 drivers/clk/eswin/Makefile                    |    8 +
 drivers/clk/eswin/clk-eic7700.c               | 1337 +++++++++++++++++
 drivers/clk/eswin/clk.c                       |  575 +++++++
 drivers/clk/eswin/common.h                    |  373 +++++
 .../dt-bindings/clock/eswin,eic7700-clock.h   |  285 ++++
 10 files changed, 2649 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
 create mode 100644 drivers/clk/eswin/Kconfig
 create mode 100644 drivers/clk/eswin/Makefile
 create mode 100644 drivers/clk/eswin/clk-eic7700.c
 create mode 100644 drivers/clk/eswin/clk.c
 create mode 100644 drivers/clk/eswin/common.h
 create mode 100644 include/dt-bindings/clock/eswin,eic7700-clock.h

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2.34.1