On Sat, 31 Jan 2026 11:26:11 -0600, Dinh Nguyen wrote:

The Cadence HP NAND Flash Controller on supports DMA transactions through
a coherent interconnect. In previous generations SoC (Stratix10 and Agilex)
the interconnect was non-coherent, hence there is no need for dma-coherent
property to be presence. In Agilex 5, the architecture has changed. It
introduced a coherent interconnect that supports cache-coherent DMA.


[...]

Applied to mtd/next, thanks!

[1/1] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property
      commit: 875382759298650c96192bf2c12e2d1e4575de92

Patche(s) should be available on mtd/linux.git and will be
part of the next PR (provided that no robot complains by then).

Kind regards,
Miquèl