[PATCH 2/2] arm: dts: lpc32xx: add interrupts property to Motor Control PWM
From: Vladimir Zapolskiy <vz@mleia.com>
Date: 2026-01-10 01:45:45
Also in:
linux-arm-kernel, linux-pwm
Subsystem:
arm/freescale imx / mxc arm architecture, arm/lpc32xx soc support, the rest · Maintainers:
Frank Li, Sascha Hauer, Vladimir Zapolskiy, Piotr Wojtaszczyk, Linus Torvalds
Motor Control PWM shares an interrupt line with TIMER4 on MIC interrupt controller, the interrupt serves as period (timer limit), pulse-width (match) and capture event interrupt. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
index 7fa91d1ac9ea..e94df78def18 100644
--- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi@@ -322,6 +322,7 @@ i2c2: i2c@400a8000 { mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_MCPWM>; #pwm-cells = <3>; status = "disabled";
--
2.43.0