Re: [PATCH v3 1/7] media: dt-bindings: Document SC8280XP/SM8350 Venus
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Date: 2026-01-30 12:29:58
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linux-arm-msm, linux-media, lkml
On 1/25/2026 9:02 PM, Dmitry Baryshkov wrote:
quoted hunk ↗ jump to hunk
From: Konrad Dybcio <konradybcio@kernel.org> Both of these SoCs implement an IRIS2 block, with SC8280XP being able to clock it a bit higher and with SM8350 having 4 VPP pipes, while SC8280XP having just 2. Document Iris2 cores found on these SoCs. Signed-off-by: Konrad Dybcio <konradybcio@kernel.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> [ bod: dropped dts video-encoder/video-decoder ] Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> [db: dropped status, dropped extra LLCC interconnect] Signed-off-by: Dmitry Baryshkov <redacted> --- .../bindings/media/qcom,sm8350-venus.yaml | 113 +++++++++++++++++++++ 1 file changed, 113 insertions(+)diff --git a/Documentation/devicetree/bindings/media/qcom,sm8350-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sm8350-venus.yaml new file mode 100644 index 000000000000..d78bdc08d830 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8350-venus.yaml@@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8350-venus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Venus video encode and decode accelerators
s/Venus/iris
+ +maintainers: + - Konrad Dybcio [off-list ref] + +description: | + The Venus Iris2 IP is a video encode and decode accelerator present + on Qualcomm platforms + +allOf: + - $ref: qcom,venus-common.yaml#
Pls remove the reference to venus-common.yaml and follow schema of sm8550-iris.yaml
+ +properties: + compatible: + enum: + - qcom,sc8280xp-venus + - qcom,sm8350-venus + + clocks: + maxItems: 3 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + + resets: + maxItems: 1 + + reset-names: + items: + - const: core
It should be named as bus not core
+
+ power-domains:
+ maxItems: 3
+
+ power-domain-names:
+ items:
+ - const: venus
+ - const: vcodec0
+ - const: mx
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: cpu-cfg
+ - const: video-mem
+
+ operating-points-v2: true
+ opp-table:
+ type: object
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - power-domain-names
+ - iommus
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,gcc-sm8350.h>
+ #include <dt-bindings/clock/qcom,sm8350-videocc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,sm8350.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ venus: video-codec@aa00000 {
+ compatible = "qcom,sm8350-venus";
+ reg = <0x0aa00000 0x100000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
+ reset-names = "core";s/core/bus following the existing YAML Thanks, Dikshita
+ + power-domains = <&videocc MVS0C_GDSC>, + <&videocc MVS0_GDSC>, + <&rpmhpd SM8350_MX>; + power-domain-names = "venus", + "vcodec0", + "mx"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + operating-points-v2 = <&venus_opp_table>; + iommus = <&apps_smmu 0x2100 0x400>; + memory-region = <&pil_video_mem>; + };