On Thu, Jan 22, 2026 at 07:40:29PM +0800, Xukai Wang wrote:

On 2026/1/19 16:18, Jiayu Du wrote:

quoted

quoted

+
+K230_CLK_GATE_FORMAT(hs_hclk_src_gate,
+		     K230_HS_HCLK_SRC_GATE,
+		     0x18, 0, 0, 0,
+		     &hs_hclk_high_src_rate.clk.hw);

Here, you replaced hs_hclk_high_gate(in v9) with hs_hclk_high_src_rate,

I'm a bit confused, as I don't recall making these specific changes.
Looking at the code below, the only difference between v9 and v10 is
within the K230_CLK_GATE_FORMAT(hs_hclk_src_gate, ...) definition, where
the second parameter changed from 1 to 0. Everything else appears
consistent. Could you clarify which change you were referring to?

quoted

but after my board test, I find that when hs_hclk_high_gate is turned
off, the mmc/sd and other high-speed subsystems can not work. So maybe
you should not change the hs_hclk_high_gate to hs_hclk_high_src_rate.

Regarding the clock management, I recommend explicitly enabling
hs_hclk_high_gateas it will be closed by `close unused clocks`.

Sorry, you are right. It was me who made the changes locally. And I
saw your reply to this email[1], which you said According to the vendor's
code, the parent clock of hs_hclk_src is hs_hclk_high_src.

Indeed, the parent clock of hs_hclk_src is hs_hclk_high_src. but
hs_hclk_high_gate is the gate of hs_hclk_high_src. So, what you mean is
that you will add the CLK_IS_CRITICAL flag to the hs_hclk_high_gate?

Link: https://lore.kernel.org/all/159615d3-cc52-43be-bf6d-5fe717ef1cc4@zohomail.com/ (local) [1]

Regards,
Jiayu Du