Re: [PATCH net-next 2/3] net: dsa: lantiq: allow arbitrary MII registers
From: Vladimir Oltean <olteanv@gmail.com>
Date: 2026-01-14 22:37:12
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On Tue, Jan 13, 2026 at 03:25:16AM +0000, Daniel Golle wrote:
quoted hunk ↗ jump to hunk
The Lantiq GSWIP and MaxLinear GSW1xx drivers are currently relying on a hard-coded mapping of MII ports to their respective MII_CFG and MII_PCDU registers and only allow applying an offset to the port index. While this is sufficient for the currently supported hardware, the very similar Intel GSW150 (aka. Lantiq PEB7084) cannot be described using this arrangement. Introduce two arrays to specify the MII_CFG and MII_PCDU registers for each port, replacing the current bitmap used to safeguard MII ports as well as the port index offset. Signed-off-by: Daniel Golle <daniel@makrotopia.org> ---diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq/lantiq_gswip.h index 8fc4c7cc5283a..b87a68a1b3b67 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq/lantiq_gswip.h@@ -253,8 +253,8 @@ struct gswip_pce_microcode { struct gswip_hw_info { int max_ports; unsigned int allowed_cpu_ports; - unsigned int mii_ports; - int mii_port_reg_offset; + s16 mii_cfg[8]; + s16 mii_pcdu[8];
Why [8] and not [7] (the larger of GSW150_PORTS and GSW1XX_PORTS)? I would prefer to see a macro holding the largest port count of the supported switches, and the "7" also expressed as that value - 1.
bool supports_2500m; const struct gswip_pce_microcode (*pce_microcode)[]; size_t pce_microcode_size;