On 06/01/2026 20:18, Krzysztof Kozlowski wrote:

On 06/01/2026 19:40, Vijay Kumar Tumati wrote:

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On 11/27/2025 12:12 AM, Krzysztof Kozlowski wrote:

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On Wed, Nov 26, 2025 at 01:38:40AM -0800, Hangxiang Ma wrote:

Look here^

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+		};
+
+		cci0: cci@ac7b000 {

Looks completely mis-ordered/sorted. What are the nodes above and below?

Hi Krzysztof, sorry, not sure how you mean exactly. The ones above are 
the pinctrl nodes. Each CCI has two masters using two GPIOs each, one 

Why would pinctrl nodes matter anyhow? Please read how DTS syntax works.

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for clk and one for data. The ones below are the actual CCI HW nodes 
that make use of the pinctrls. I believe this is inline with previous 
generations. Have I missed something? Thanks.

I wrote what is wrong. Is this maintaining proper sorting? Did you read
DTS coding style?

Heh, you received my review 1 day after your posting.

You replied to my review 5-6 weeks after, yet you still expect me to
understand the context and provide clarifications.

There is simpler way: NAK.

You will not get your patches merged with such latency and such replies
not even trying to address the problem or learn about it.

Best regards,
Krzysztof