Re: [PATCH v8 13/18] media: ti: j721e-csi2rx: add multistream support

Hi,

On 09/12/2025 12:36, Jai Luthra wrote:

Hi Rishikesh,

Quoting Rishikesh Donadkar (2025-12-09 15:38:33)

quoted

On 01/12/25 18:33, Tomi Valkeinen wrote:

quoted

Hi,

Hi Tomi,

Thank you for the review !

quoted

On 12/11/2025 13:54, Rishikesh Donadkar wrote:

quoted

From: Jai Luthra <redacted>

Each CSI2 stream can be multiplexed into 4 independent streams, each

Well, that's not true, at least generally speaking (there can be more
than 4). Is that specific to TI hardware?

Yes, The commit message talks about how TI CSI does the multiplexing of 
CSI stream from the sensor into 4 streams as show in the Figure 12-388 
in AM62A TRM[1]. I will modify the commit message to mention that this 
is TI CSI specific.

Figure 12-388 shows the internal pixel stream coming from Cadence to
different hardware blocks like TI's Shim (DMA) and VP0 (ISP) and VP1. I
don't see that being related to CSI2 VC/DT support, which is handled by the
Shim using different DMA contexts and channels.

In the TRM, under 12.6.1.1.1 CSI_RX_IF Features, I see:
 * Compliant to MIPI CSI v1.3
 * Supports up to 16 virtual channels per input (partial MIPI CSI v2.0 feature)

So 16 VCs is supported by TI's CSI pipeline, despite it being MIPI CSI2
v1.3 compliant otherwise. I think I might have been confused with DS90UB960
while writing this commit message originally, which strictly supports a
maximum of 4 VCs.

Secondly, even with just CSI2 v1.0 compliant source, this could
theoretically handle 8 "streams" of data with 4 different VCs x 2 data
types each. So please update the paragraph in next revision.

Where does the "8" come from? Do we have 8 context registers, to which
we program the VC + DT filter?

Also, it could as well be 8 streams, all with VC 0, but each different
DT (probably unlikely scenario =). But I just want to highlight that VC
is not the "stream". The "stream" is the VC+DT tuple.

 Tomi