Re: [PATCH 3/5] clk: qcom: cmnpll: Add IPQ5332 SoC support

On 12/4/2025 9:48 PM, Konrad Dybcio wrote:

On 12/4/25 9:09 AM, Jie Luo wrote:

quoted

On 12/1/2025 9:52 PM, Konrad Dybcio wrote:

quoted

On 11/28/25 9:40 AM, Luo Jie wrote:

quoted

The CMN PLL in IPQ5332 SoC produces different output clocks when compared
to IPQ9574. While most clock outputs match IPQ9574, the ethernet PHY/switch
(50 Mhz) and PPE clocks (200 Mhz) in IPQ5332 are different.

Add IPQ5332-specific clock definitions and of_device_id entry.

Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
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[...]

quoted

+static const struct cmn_pll_fixed_output_clk ipq5332_output_clks[] = {
+	CLK_PLL_OUTPUT(IPQ5332_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
+	CLK_PLL_OUTPUT(IPQ5332_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
+	CLK_PLL_OUTPUT(IPQ5332_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
+	CLK_PLL_OUTPUT(IPQ5332_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL),
+	CLK_PLL_OUTPUT(IPQ5332_PPE_200MHZ_CLK, "ppe-200mhz", 200000000UL),
+	CLK_PLL_OUTPUT(IPQ5332_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL),

I can't really find the source for most of these, but I see that there's both
a 200 and a 300 MHz output to NSS

Konrad

Both IPQ5332_XO_24MHZ_CLK and IPQ5332_SLEEP_32KHZ_CLK are intended to be
used as the input clocks to the GCC block. IPQ5332_PCS_31P25MHZ_CLK
provides the reference clock for the Ethernet PCS, and
IPQ5332_ETH_50MHZ_CLK is the source clock for the PCS PLL on IPQ5332.
On this platform the Ethernet clocking path is:
CMN PLL ETH 50 MHz output → PCS PLL (divider + gate) → attached PHY or
switch.

What about that 200 MHz NSS output? Is it just renamed to PPE?

Konrad

On the IPQ5332 platform, the PPE operates at 200 MHz.
IPQ5332_PPE_200MHZ_CLK is the 200 MHz reference clock for the Packet
Processing Engine (PPE), sourced via the NSS clock controller.

The IPQ5332_NSS_300MHZ_CLK refers to the 300 MHz clock that is supplied
to other NSS blocks, for example, crypto (EIP) block. This is also
sourced via the NSS clock controller.