-----Original Message-----
From: Biju Das <biju.das.jz@bp.renesas.com>
Sent: 22 November 2025 13:49
Subject: RE: [PATCH v3 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

Hi Geert,

Thanks for the feedback.

quoted

-----Original Message-----
From: Geert Uytterhoeven <geert@linux-m68k.org>
Sent: 21 November 2025 16:29
Subject: Re: [PATCH v3 01/13] dt-bindings: serial: renesas,rsci:
Document RZ/G3E support

Hi Biju,

On Fri, 14 Nov 2025 at 11:52, Biju [off-list ref] wrote:

quoted

From: Biju Das <biju.das.jz@bp.renesas.com>

Add documentation for the serial communication interface (RSCI)
found on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC
is identical to that on the RZ/T2H (R9A09G077) SoC, but it has a
32-stage FIFO compared to 16 on RZ/T2H. It supports both FIFO and
non-FIFO mode operation. RZ/G3E has 6 clocks(5 module clocks + 1
external clock) compared to 3 clocks
(2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

quoted

--- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml

@@ -10,17 +10,16 @@ maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

-allOf:
-  - $ref: serial.yaml#
-
 properties:
   compatible:
     oneOf:
-      - items:
-          - const: renesas,r9a09g087-rsci # RZ/N2H
-          - const: renesas,r9a09g077-rsci # RZ/T2H
+      - enum:
+          - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
+          - renesas,r9a09g047-rscif # RZ/G3E FIFO mode

I can't find the non-FIFO ports in the documentation?
Do you mean "Selectable to 1-stage register or 32-stage FIFO"?
Isn't that software configuration instead of hardware description?

Basically, it has 2 modes. FIFO mode(CCR3.FM=1b) and Non-FIFO mode (CCR3.FM=0b).
DMAC can be used only in FIFO mode and there are some hardware differences between two as FIFO reg
block is applicable only for FIFO mode.

It has to be either a compatible or a boolean property "renesas, rsci-non-fifo"
Or something else

I believe it must be a compatible to support non-FIFO mode from boot.

I maybe wrong. Please correct me, if it I am wrong.

Cheers,
Biju