[PATCH v4 5/5] arm64: dts: renesas: R8A78000: Add initial Ironhide support
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Date: 2025-09-17 05:31:17
Also in:
linux-arm-kernel, linux-perf-users, linux-renesas-soc
Subsystem:
arm/risc-v/renesas architecture, the rest · Maintainers:
Geert Uytterhoeven, Magnus Damm, Linus Torvalds
From: Hai Pham <redacted> Add the initial support for Renesas X5H Ironhide board. Note: It is using "maxcpus" in bootargs to limit number of CPU, because SMP support is now under development. This limitation will be removed in the future. [Kuninori: tidyup for upstreaming] Signed-off-by: Hai Pham <redacted> Signed-off-by: Vinh Nguyen <redacted> Signed-off-by: Takeshi Kihara <redacted> Signed-off-by: Khanh Le <redacted> Signed-off-by: Huy Bui <redacted> Signed-off-by: Phong Hoang <redacted> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../boot/dts/renesas/r8a78000-ironhide.dts | 92 +++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index ccdf7aaeca13e..dde046a3f25c8 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile@@ -136,6 +136,8 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb r8a779m5-salvator-xs-panel-aa104xd12-dtbs := r8a779m5-salvator-xs.dtb salvator-panel-aa104xd12.dtbo dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs-panel-aa104xd12.dtb +dtb-$(CONFIG_ARCH_R8A78000) += r8a78000-ironhide.dtb + dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
new file mode 100644
index 0000000000000..29b7180cabbcd
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts@@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Ironhide board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a78000.dtsi" + +/ { + model = "Renesas Ironhide board based on r8a78000"; + compatible = "renesas,ironhide", "renesas,r8a78000"; + + aliases { + serial0 = &hscif0; + }; + + chosen { + /* + * REMOVE-ME + * + * It works 1 CPU core only for now. This limitation will be + * removed in future. + */ + bootargs = "maxcpus=1"; + stdout-path = "serial0:1843200n8"; + }; + + memory@60600000 { + device_type = "memory"; + /* first 518MiB is reserved for other purposes. */ + reg = <0x0 0x60600000 0x0 0x5fa00000>; + }; + + memory@1080000000 { + device_type = "memory"; + reg = <0x10 0x80000000 0x0 0x80000000>; + }; + + memory@1200000000 { + device_type = "memory"; + reg = <0x12 0x00000000 0x1 0x00000000>; + }; + + memory@1400000000 { + device_type = "memory"; + reg = <0x14 0x00000000 0x1 0x00000000>; + }; + + memory@1600000000 { + device_type = "memory"; + reg = <0x16 0x00000000 0x1 0x00000000>; + }; + + memory@1800000000 { + device_type = "memory"; + reg = <0x18 0x00000000 0x1 0x00000000>; + }; + + memory@1a00000000 { + device_type = "memory"; + reg = <0x1a 0x00000000 0x1 0x00000000>; + }; + + memory@1c00000000 { + device_type = "memory"; + reg = <0x1c 0x00000000 0x1 0x00000000>; + }; + + memory@1e00000000 { + device_type = "memory"; + reg = <0x1e 0x00000000 0x1 0x00000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666600>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + uart-has-rtscts; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <26000000>; +};
--
2.43.0