Re: [PATCH 1/3 v2] dt-bindings: PCI: s32g: Add NXP PCIe controller
From: Manivannan Sadhasivam <mani@kernel.org>
Date: 2025-09-22 06:21:19
Also in:
imx, linux-arm-kernel, linux-pci, lkml
On Fri, Sep 19, 2025 at 05:58:19PM +0200, Vincent Guittot wrote:
Describe the PCIe controller available on the S32G platforms.
You should mention that this binding is for the controller operating in 'Root Complex' mode.
quoted hunk ↗ jump to hunk
Co-developed-by: Ionut Vicovan <redacted> Signed-off-by: Ionut Vicovan <redacted> Co-developed-by: Bogdan-Gabriel Roman <redacted> Signed-off-by: Bogdan-Gabriel Roman <redacted> Co-developed-by: Larisa Grigore <redacted> Signed-off-by: Larisa Grigore <redacted> Co-developed-by: Ghennadi Procopciuc <redacted> Signed-off-by: Ghennadi Procopciuc <redacted> Co-developed-by: Ciprian Marian Costea <redacted> Signed-off-by: Ciprian Marian Costea <redacted> Co-developed-by: Bogdan Hamciuc <redacted> Signed-off-by: Bogdan Hamciuc <redacted> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> --- .../devicetree/bindings/pci/nxp,s32-pcie.yaml | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32-pcie.yamldiff --git a/Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml b/Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml new file mode 100644 index 000000000000..cabb8b86c042 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml@@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/nxp,s32-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2xx/S32G3xx PCIe controller + +maintainers: + - Bogdan Hamciuc <bogdan.hamciuc@nxp.com> + - Ionut Vicovan <ionut.vicovan@nxp.com> + +description: + This PCIe controller is based on the Synopsys DesignWare PCIe IP. + The S32G SoC family has two PCIe controllers, which can be configured as + either Root Complex or Endpoint. +
But this binding is going to cover only the 'Root Complex' mode, isn't it?
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nxp,s32g2-pcie # S32G2 SoCs RC mode
+ - items:
+ - const: nxp,s32g3-pcie
+ - const: nxp,s32g2-pcie
+
+ reg:
+ maxItems: 7
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: dbi2
+ - const: atu
+ - const: dma
+ - const: ctrl
+ - const: config
+ - const: addr_space
+
+ interrupts:
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: link-req-stat
+ - const: dma
+ - const: msi
+ - const: phy-link-down
+ - const: phy-link-up
+ - const: misc
+ - const: pcs
+ - const: tlp-req-no-comp
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - ranges
+ - phys
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/phy/phy.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@40400000 {
+ compatible = "nxp,s32g3-pcie",
+ "nxp,s32g2-pcie";
+ reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi registers */
+ <0x00 0x40420000 0x0 0x00001000>, /* dbi2 registers */
+ <0x00 0x40460000 0x0 0x00001000>, /* atu registers */
+ <0x00 0x40470000 0x0 0x00001000>, /* dma registers */
+ <0x00 0x40481000 0x0 0x000000f8>, /* ctrl registers */
+ /*
+ * RC configuration space, 4KB each for cfg0 and cfg1
+ * at the end of the outbound memory map
+ */
+ <0x5f 0xffffe000 0x0 0x00002000>,
+ <0x58 0x00000000 0x0 0x40000000>; /* 1GB EP addr space */
+ reg-names = "dbi", "dbi2", "atu", "dma", "ctrl",
+ "config", "addr_space";
+ dma-coherent;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges =
+ /*
+ * downstream I/O, 64KB and aligned naturally just
+ * before the config space to minimize fragmentation
+ */
+ <0x81000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>,s/0x81000000/0x01000000 since the 'relocatable' is irrelevant.
+ /* + * non-prefetchable memory, with best case size and + * alignment + */ + <0x82000000 0x0 0x00000000 0x58 0x00000000 0x7 0xfffe0000>;
s/0x82000000/0x02000000 And the PCI address really starts from 0x00000000? I don't think so. - Mani -- மணிவண்ணன் சதாசிவம்