On Wed, Sep 10, 2025 at 10:08:39AM +0800, Chen Wang wrote:

From: Chen Wang <redacted>

Add support for PCIe controller in SG2042 SoC. The controller
uses the Cadence PCIe core programmed by pcie-cadence*.c. The
PCIe controller will work in host mode only, supporting data
rate(gen4) and lanes(x16 or x8).

Strictly speaking, "gen4" is a spec revision, not a data rate.
Include the GT/s rate instead or in addition.  We can fix this when
merging if there's no other reason to repost (I assume you mean 16
GT/s).  Will also add spaces before the open "(".