[PATCH v2 18/23] staging: media: tegra-video: tegra20: increase maximum VI clock frequency
From: Svyatoslav Ryhel <hidden>
Date: 2025-09-06 13:54:32
Also in:
dri-devel, linux-clk, linux-media, linux-staging, linux-tegra, lkml
Subsystem:
media input infrastructure (v4l/dvb), staging subsystem, tegra video driver, the rest · Maintainers:
Mauro Carvalho Chehab, Greg Kroah-Hartman, Thierry Reding, Jonathan Hunter, Sowjanya Komatineni, Luca Ceresoli, Linus Torvalds
Increase maximum VI clock frequency to 450MHz to allow correct work with high resolution camera sensors. Signed-off-by: Svyatoslav Ryhel <redacted> --- drivers/staging/media/tegra-video/tegra20.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/media/tegra-video/tegra20.c
index e0da496bb50f..3c5bafebfcd8 100644
--- a/drivers/staging/media/tegra-video/tegra20.c
+++ b/drivers/staging/media/tegra-video/tegra20.c@@ -590,7 +590,7 @@ const struct tegra_vi_soc tegra20_vi_soc = { .ops = &tegra20_vi_ops, .hw_revision = 1, .vi_max_channels = 2, /* TEGRA_VI_OUT_1 and TEGRA_VI_OUT_2 */ - .vi_max_clk_hz = 150000000, + .vi_max_clk_hz = 450000000, .has_h_v_flip = true, };
--
2.48.1