[PATCH v2 1/4] clk: tegra20: reparent dsi clock to pll_d_out0
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STALE399d
SUPERSEDED
From: Svyatoslav Ryhel <hidden>
Date: 2025-09-06 13:17:17
Also in:
dri-devel, linux-clk, linux-tegra, lkml
Subsystem:
common clk framework, tegra clock driver, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Prashant Gaikwad, Linus Torvalds
Revision v2 of 6 in this series.
Revisions (6)
Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD. Signed-off-by: Svyatoslav Ryhel <redacted> --- drivers/clk/tegra/clk-tegra20.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index bf9a9f8ddf62..9160f27a6cf0 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c@@ -801,9 +801,9 @@ static void __init tegra20_periph_clk_init(void) clks[TEGRA20_CLK_MC] = clk; /* dsi */ - clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, - 48, periph_clk_enb_refcnt); - clk_register_clkdev(clk, NULL, "dsi"); + clk = tegra_clk_register_periph_gate("dsi", "pll_d_out0", 0, + clk_base, 0, TEGRA20_CLK_DSI, + periph_clk_enb_refcnt); clks[TEGRA20_CLK_DSI] = clk; /* csus */
--
2.48.1