[PATCH v3 04/11] arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS
From: Anand Moon <hidden>
Date: 2025-09-05 11:59:18
Also in:
linux-amlogic, linux-arm-kernel, lkml
Subsystem:
arm/amlogic meson soc support, the rest · Maintainers:
Neil Armstrong, Kevin Hilman, Linus Torvalds
As per the AXG datasheet add missing cache information to the Amlogic AXG SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Signed-off-by: Anand Moon <redacted> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 2df143aa77ce3..04fb130ac7c6a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi@@ -83,6 +83,12 @@ cpu1: cpu@1 { compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>;
@@ -94,6 +100,12 @@ cpu2: cpu@2 { compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>;
@@ -105,6 +117,12 @@ cpu3: cpu@3 { compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>;
@@ -115,6 +133,9 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; };
--
2.50.1