On 9/4/25 7:32 PM, Dmitry Baryshkov wrote:

On Thu, Sep 04, 2025 at 04:34:05PM +0200, Konrad Dybcio wrote:

quoted

On 9/4/25 3:35 PM, Dmitry Baryshkov wrote:

quoted

On Wed, Sep 03, 2025 at 09:58:33PM +0530, Wasim Nazir wrote:

quoted

On Wed, Sep 03, 2025 at 06:12:59PM +0200, Konrad Dybcio wrote:

quoted

On 8/27/25 3:20 AM, Dmitry Baryshkov wrote:

quoted

On Tue, Aug 26, 2025 at 11:51:01PM +0530, Wasim Nazir wrote:

quoted

From: Monish Chunara <redacted>

Introduce the SDHC v5 controller node for the Lemans platform.
This controller supports either eMMC or SD-card, but only one
can be active at a time. SD-card is the preferred configuration
on Lemans targets, so describe this controller.

Define the SDC interface pins including clk, cmd, and data lines
to enable proper communication with the SDHC controller.

Signed-off-by: Monish Chunara <redacted>
Co-developed-by: Wasim Nazir <redacted>
Signed-off-by: Wasim Nazir <redacted>
---
 arch/arm64/boot/dts/qcom/lemans.dtsi | 70 ++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 99a566b42ef2..a5a3cdba47f3 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi

@@ -3834,6 +3834,36 @@ apss_tpdm2_out: endpoint {
 			};
 		};
 
+		sdhc: mmc@87c4000 {
+			compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x0 0x087c4000 0x0 0x1000>;
+
+			interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>;
+			clock-names = "iface", "core";
+
+			interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>,
+					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>;
+			interconnect-names = "sdhc-ddr", "cpu-sdhc";
+
+			iommus = <&apps_smmu 0x0 0x0>;
+			dma-coherent;
+
+			resets = <&gcc GCC_SDCC1_BCR>;
+
+			no-sdio;
+			no-mmc;
+			bus-width = <4>;

This is the board configuration, it should be defined in the EVK DTS.

Unless the controller is actually incapable of doing non-SDCards

But from the limited information I can find, this one should be able
to do both

It’s doable, but the bus width differs when this controller is used for
eMMC, which is supported on the Mezz board. So, it’s cleaner to define
only what’s needed for each specific usecase on the board.

`git grep no-sdio arch/arm64/boot/dts/qcom/` shows that we have those
properties inside the board DT. I don't see a reason to deviate.

Just to make sure we're clear

I want the author to keep bus-width in SoC dt and move the other
properties to the board dt

I think bus-width is also a property of the board. In the end, it's a
question of schematics whether we route 1 wire or all 4 wires. git-log
shows that bus-width is being sent in both files (and probalby we should
sort that out).

Actually this is the controller capability, so if it can do 8, it should
be 8 and the MMC core will do whatever it pleases (the not-super-sure
docs that I have say 8 for this platform)

Konrad