On 9/4/25 12:52 PM, Krzysztof Kozlowski wrote:

On 04/09/2025 12:51, Krzysztof Kozlowski wrote:

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On 04/09/2025 10:36, Konrad Dybcio wrote:

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On 9/3/25 10:21 AM, 'Krzysztof Kozlowski' via kernel wrote:

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On 03/09/2025 10:04, Sarthak Garg wrote:

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Due to board-specific hardware constraints particularly related
to level shifter in this case the maximum frequency for SD High-Speed
(HS) mode must be limited to 37.5 MHz to ensure reliable operation of SD
card in HS mode.

This is achieved by introducing the `max-sd-hs-hz` property in the
device tree, allowing the controller to operate within safe frequency
limits for HS mode.

Probably we will now replicate the same discussion... And it will be
happening every time you send the same and not reflect it in commit msg.

Just to emphasize this - it will happen EVERY time.

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Bindings say board setup, this commit msg says board config, but the
patch says SoC. This is not correct.

Both are correct, looking at the problem from two perspectives.

The bindings description mentions board-specific limitations (e.g. because
"the board's electrical design does not allow one to achieve the full rated
frequency that the SoC can otherwise do, in a stable way")

Here the author tries to argue that almost all SM8550 boards are broken
in this sense, because the reference design did not feature the required
passive components, making most (derivative) designs sort of "broken by
default" - and only some (if any?) vendors decided to go with the
additional components required to lift this limitation.

This in turn makes it fair to assume the developer experience would benefit
from having the SD card high speed modes always work (with the slight speed
cap which may not be required for the 1 or 2 designs that took the extra
step) without each board DT creator having to track down this property
separately.

And then if you send same v3, I will ask the same. Can the author

v3 -> v6

So, would you be accepting of this patch if the commit message was:

arm64: dts: qcom: sm8550: Limit max SD HS mode frequency by default

Due to an implementation detail in this SoC, additional passive
electrical components are required to achieve the maximum rated speed
of the SD controller when paired with a High-Speed SD Card. Without them,
the clock frequency must be limited to 37.5 MHz for link stability.

Because the reference design does not contain these components, most
(derivative) boards do not have them either. To accommodate for that,
apply the frequency limit by default and delegate lifting it to the
odd boards that do contain the necessary onboard hardware.

Konrad