[PATCH v5 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
From: Laura Nao <hidden>
Date: 2025-08-29 09:21:06
Also in:
linux-arm-kernel, linux-clk, linux-mediatek, lkml, netdev
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
On MT8196, some clocks use one register for parent selection and gating, and a separate register for frequency division. Since composite clocks can combine a mux, divider, and gate in a single entity, add a macro to simplify registration of such clocks by combining parent selection, frequency scaling, and enable control into one definition. Reviewed-by: Nícolas F. R. A. Prado <redacted> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Laura Nao <redacted> --- drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c381d6a6d908..5417b9264e6d 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h@@ -175,6 +175,25 @@ struct mtk_composite { .flags = 0, \ } +#define MUX_DIV_GATE(_id, _name, _parents, \ + _mux_reg, _mux_shift, _mux_width, \ + _div_reg, _div_shift, _div_width, \ + _gate_reg, _gate_shift) { \ + .id = _id, \ + .name = _name, \ + .parent_names = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .mux_reg = _mux_reg, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .divider_reg = _div_reg, \ + .divider_shift = _div_shift, \ + .divider_width = _div_width, \ + .gate_reg = _gate_reg, \ + .gate_shift = _gate_shift, \ + .flags = CLK_SET_RATE_PARENT, \ + } + int mtk_clk_register_composites(struct device *dev, const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock,
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2.39.5